Quantum error correction at QCE26 became a race for the decoder

This guide follows 46 error-correction talks at IEEE Quantum Week 2026 in Toronto. Most of them dwelt on the classical machines that must keep up with the qubits.

On the afternoon of Monday 14 September, at the end of a tutorial in Room 716A of the Metro Toronto Convention Centre, Daniel Bulmash of IQM put up a sum. A useful quantum computer might hold 10,000 logical qubits, the reliable qubits a program sees. Each needs about 50 checks a microsecond. That makes a stream of 500 gigabits a second, and some ordinary computer has to read all of it, decide what went wrong and send back a fix before the next microsecond starts. The programs that do that job are called quantum error correction decoders.

That stream, and the clock it runs against, is what quantum error correction is now about. Qubits fail often. Even good hardware gets about one step in a thousand wrong, while a program that could break RSA encryption needs about a trillion steps without a slip. So error correction spreads each logical qubit across many physical qubits and checks them over and over. A classical program called a decoder reads which checks failed and works out the most likely fault, much as a mechanic reads the warning lights on a dashboard.

The 46 talks followed here, from IEEE Quantum Week 2026, known as QCE26, pointed one way. Taken together they suggest the qubits are no longer the only thing holding error correction back, and that the harder half is now the classical machinery that must read them, decide and answer before the clock ticks again. The industry has not agreed who builds it. Nor has it agreed how the parts should talk to each other.

The best case against that view came from the hardware. On the Monday evening Rajeeb Hazra, chief executive of Quantinuum, reported a logical memory on the company’s Helios machine that fails about 4.6 times in 100,000 rounds for each qubit. That is good, and it is still far from what a trillion-step program needs, so better qubits remain the first job. On the Wednesday, panellists from IonQ and Oratomic said trapped ions and neutral atoms run so slowly that their decoders have time to spare. On that reading the qubits are still the limit, and the race against the microsecond clock belongs to superconducting chips alone. It is a fair point, and for ions and atoms it may hold for years.

The superconducting groups ran that race anyway. A team from the University of Tokyo designed decoding logic that spends well under a microsecond on each round. Alessio Cicero of Chalmers squeezed a neural network decoder onto a chip that can be rewired in software, inside the same time budget. IBM’s Blake Johnson said the firm had dropped FPGAs for chips of its own, since real programs would need hundreds of FPGA images. Xiaodi Wu of the University of Maryland went further still and timed the whole electronic loop, with the signal looped back in place of a chip, at 446 billionths of a second. No other talk timed a whole superconducting loop.

The new codes told a similar story. Kun Liu said IBM’s 144-qubit bicycle code does the work of a surface code about ten times its size, and Jason Chadwick sought a similar saving for silicon spin qubits. Both gains come at a price. They need long links across the chip and careful schedules, and each code needs a decoder of its own, which puts still more weight on the classical side. Chadwick’s codes lost to the plain surface code at the shuttle error rates Chadwick expects soon.

Even the tool behind most of these numbers came under fire. Seokhyeon Son of Yonsei University trained eight learning decoders in simulation and then ran them on IBM chips and an IonQ emulator. The league table largely flipped. The decoders that looked best in simulation tended to do worse on the machines, and the two that trailed in simulation were the only ones that did no harm on every machine they met.

Yet the hardest deadline may be commercial. A decoder is useless unless the control electronics feed it on time, and the two usually come from different firms. At Thursday’s panel on interfaces, Moritz Kirste of Zurich Instruments described a jungle of one-to-one deals between control firms and decoder makers, and Adam Paetznick of Microsoft said it may be too early for a standard. Hazra’s call to retire quantum volume for a new score Hazra calls QUOPS, which counts speed as well as size, made the same point from the other end. Whoever writes the yardstick shapes the race.

Decoders racing a one-microsecond clock

A surface code, the standard way to lay out error correction, measures its checks in rounds that last about a microsecond each on a superconducting chip. If the decoder takes longer than that on average, unread rounds pile up behind it and the errors win. Ten talks went at that deadline from ten sides.

Tokyo cuts the time per round by a third

A team from the University of Tokyo said it had drawn up the first hardware design for a trick called sandwich decoding. The authors were Leo Itoh, Takuya Kasamura, Hidetsugu Irie and Junichiro Kadomoto. The trick, set out in 2023 by Tan and colleagues, cuts the history of checks into windows that overlap, decodes them side by side and then stitches the seams. Until now, the speaker said, it had only run in software.

Their design runs two fast window decoders, built on a quick method called union-find, plus a small stage for the seams. They tested it in simulation for 22 and 7 nanometre chips. At distance 21 and a 1 percent error rate, the time per round fell from 186.7 to 122.1 nanoseconds, a cut of about 35 percent, while the chip area grew from 2.54 to 3.51 square millimetres. No chip was made. Each design is also fixed to one code size.

RIKEN spreads one decoder across many chips

Jan-Erik Wichmann of RIKEN designed a matching decoder whose data flows one way only, which lets it spread across many FPGAs, the chips that can be rewired for fast logic. Their co-authors were Werner Florian Samayoa, Prasoon Ambalathankandy and Kentaro Sano, and the paper won a best-paper award in the QTEM track. Links between FPGAs are about 100 times slower than links inside one, Wichmann said. So a design that trades data back and forth cannot grow.

A grid of small processors first prunes the graph of errors. Matching units then search for the lightest way to pair up what is left, and the decoder found the exact answer at distance 5 in all 1,000 test cases. The cost climbs fast. Wichmann put it at about five FPGAs for distance 7 and about 3,000 for distance 9, all for one logical qubit.

RIKEN finds the links between chips too slow

Kentaro Sano of the RIKEN Center for Computational Science took the same decoder from paper to cluster. Sano works in Japan’s Moonshot Goal 6 programme, where about 20 groups are building error correction for superconducting qubits, and RIKEN’s part is the decoders. Sano framed the job as reaction time. That is the wait from reading a magic state to knowing whether a fix must follow.

The plan splits the work into stages that only pass data forward, so one FPGA prunes the graph and many others test candidate pairings while a leaderboard keeps the best. The weak point is the wire. On RIKEN’s cluster one hop between FPGAs took a median of 606 nanoseconds, and Sano wants tens of nanoseconds, perhaps from a simpler link. A first test joining a controller from a Japanese start-up to two FPGAs is still being analysed.

NVIDIA clears the easy errors first

Muyuan Li of NVIDIA showed a neural pre-decoder. It is a learned filter that clears away most of the error signals before a standard decoder sees them. Their network looks at a small patch of the code at a time and guesses the physical fixes, and whatever is left over goes to a standard tool such as PyMatching or Chromobius. One consumer graphics card can train a good model up to distance 9, Li said.

One model of about 7 million settings, trained at a single code size, worked on colour codes from distance 5 to 31. At distance 31 it cut the logical error rate by a factor of about 348 and decoded about seven times faster, though small codes could run slower. Li said every result published so far holds a qubit idle in memory. Decoding a code while it runs logic is still open.

Chalmers fits a neural decoder inside the deadline

Alessio Cicero of Chalmers took a graph neural network decoder from about 700 microseconds a run to under one microsecond. Cicero worked with Luigi Altamura and Pedro Trancoso of Chalmers and with Moritz Lange and Mats Granath in Gothenburg. The team made three changes. They pruned the network, put a cap on the size of the input graph and tightened the path the data takes through the chip.

One pruned network is 9.2 times smaller and still makes 21 percent fewer logical errors than standard matching at distance 7. On an Alveo U250 board the worst case took 988.8 nanoseconds, so every graph it supports meets the deadline. Cicero was clear on the limits. The figure covers only the network’s own answer, and building the graph and talking to the controller both sit outside it.

ADaPT lets the window grow when the decoder is unsure

Joshua Viszlai presented ADaPT on behalf of Tina Oberoi, who could not attend, for a paper with Frederic Chong. Decoders usually work on a fixed number of rounds at a time, and a big window is accurate but slow, which forces a choice between getting it right and keeping up. ADaPT keeps the window small while the decoder is sure of itself. It grows only when needed.

On a toric code at distance 7, the adaptive decoder matched the error rate of a full window at about 0.4 to 0.6 times the decoding time. A bicycle code recovered its target in the same way. Viszlai said 20 to 30 percent of windows need a second try, and that the best starting size depends on the code.

Aalto makes belief propagation work on the surface code alone

Alexandru Paler of Aalto University got a fast, cheap decoder to work on the surface code without a heavier partner. Paler worked with Pedro Hack, Luca Menti and Francisco Lázaro. Belief propagation passes messages around the graph of checks. On the surface code it shows no threshold, so it has always been paired with a slower method called matching, which finds the lightest way to pair up the failed checks.

The group runs it on the matching graph instead and adds extra checks that force chosen edges to settle. After 25 iterations it reached a threshold under the simple noise model in which only data qubits fail. That costs some accuracy. At distance 11 it was about ten times worse than matching. Paler said it ran up to about a hundred times faster than PyMatching over a million decodes. Paler also argued that real time needs two kinds of deadline, hard ones where a single miss is a failure and soft ones that may slip now and then.

DLR calls the slow decoder far less often

Luca Menti, a doctoral student at the German Aerospace Center (DLR), cut calls to a costly matching decoder by up to 10,000 times on toric codes at distances 8 and 10, with no loss in accuracy. Menti worked with Francisco Lázaro. A two-stage scheme called belief matching runs belief propagation first and calls matching only when it fails. On these codes it fails often.

Menti gave every message in the first stage a weight that can be trained, so that it settles on its own far more often, and adding redundant checks gave the 10,000-fold cut. To keep training cheap, one small patch of shared weights was tiled across the lattice, holding the count at 6,608 at every distance. Weights trained at distance 4 worked at distance 10. A surface-code version is in progress, and circuit-level noise comes next.

Maryland times the whole electronic loop at 446 nanoseconds

Xiaodi Wu of the University of Maryland timed the whole loop, from the readout electronics, through the decoder and back out as a signal to the chip. Earlier talks had timed the decoder on its own. Wu spoke for Junyi Liu, Yi Lee, Yilun Xu and Gang Huang, with a co-author at Lawrence Berkeley National Laboratory. The system is open source and runs on three boards.

At distance 3, with the radio signal looped straight back, the system took 446 nanoseconds with an observed variation of 99 nanoseconds, and Wu’s chart drew the line at 1.1 microseconds, putting their design well on the fast side. A projection from measured delays stretches the same speed to 881 qubits at distance 21. Nobody has built that larger system yet.

A decoder for codes stored in an oscillator

Anders Buvarp of the Norwegian University of Science and Technology wants a decoder for bosonic codes small enough for an FPGA. Buvarp worked with Stefan Werner of NTNU and Aalto University. A bosonic code such as GKP stores a qubit in the motion of an oscillator, laid out as points on a grid. Noise nudges a point off the grid. The decoder must work out the nudge, and fast.

So far Buvarp has tested a stand-in task. Buvarp rebuilt an entangled two-qubit state from noisy measurements, and a network built on quaternions, a number system with four parts, did best as noise and wild outliers grew. One version took about 443 nanoseconds per example in software. The full decoder and the FPGA build are still to come.

Codes that need fewer qubits

The surface code is forgiving and expensive. A good logical qubit can need hundreds of physical ones, which is why a newer family called qLDPC codes, short for quantum low-density parity-check, draws so much interest. They promise the same protection from far fewer qubits. The price is checks that join qubits far apart on the chip. Eight talks worked on these codes, on rival ways to save qubits and on the chips that would run them.

A programmable torus for IBM’s bicycle code

Kun Liu set IBM’s 144-qubit gross bicycle code, which holds 12 logical qubits at distance 12, against a surface code that needs 1,452 qubits for 12 at distance 11. The catch is that each check touches two distant qubits. The usual answer builds every long link into the chip before it is cooled. Liu’s co-authors included Robert J Schoelkopf and Yongshan Ding.

Liu proposes a network shaped like a doughnut, or torus, where a long-range gate is made by passing a state through neighbours. That cut the long-range couplers from 324 to 36. Total wiring length fell by 14.1 to 38.0 percent. A check meant to flag where errors happened proved costly, runs without it did better, and Liu said a better decoder for flagged errors is still needed.

Spin qubits pay off only with better shuttles

Jason Chadwick did this work with Frederic Chong at the University of Chicago, before Chadwick moved to Atom Computing. Chadwick ran qLDPC codes on SpinBus, a 2024 design for spin qubits in tiled cells. Tracks join the cells, and electrons are moved along them. Such codes can be about ten times more space efficient than the surface code, Chadwick said, as long as the helper qubits can move between data qubits without crashing on tracks that have one lane.

One trick wraps each shuttle in Hadamard gates, so that a stray error turns into a wrong helper reading instead of two errors on the data. Chadwick said that makes the circuit ten times more tolerant of shuttle noise. A path planner borrowed from warehouse robots needed 12 percent more shuttles than an ideal plan. At a shuttle error of one in 100 per cell, which Chadwick expects in the near term, no qLDPC code beat the surface code, while below that the bicycle code made about a hundred times fewer logical errors.

IonQ’s walking cats put 110 logical qubits on 2,514 ions

Edwin Tham of IonQ set out a trapped-ion design built, IonQ says, only from parts it has already shown. Ions move only in fixed loops of three sizes. That suits the cyclic shape of the bicycle codes the walking-cat architecture uses, and the design assumes two-qubit gate errors of 1 in 10,000, a level Tham said IonQ has reached on test beds. Its memory code, nicknamed Totoro after the large cat in the Miyazaki film, holds 22 logical qubits in 102 physical ones at distance 9.

All logic runs as measurements made with cat states, superpositions of all zeros and all ones. In simulation Tham’s group found that one round of checks between measurements is enough, where the literature had assumed about one per unit of distance. IonQ’s table offers 110 logical qubits and a million T gates a day on 2,514 physical qubits. That will not break RSA, Tham said. The main risk is cooling, since cooling harder slows the cycle.

Snakes on a silicon plane

Julian Shen of the Technical University of Munich wrote routing methods for logical qubits on a silicon spin chip. Ludwig Schmid and Robert Wille worked with them. In the layout Shen used, each logical qubit is a line of physical qubits, called a snake. A snake waits on one kind of grid edge to keep its code running, and travels along another kind when it has to take part in a gate.

Shen’s routing books space ahead of each move so no two snakes collide. One family of methods used fewer time steps and another used fewer moves, and only the second kept working once the grid was packed full of snakes. With 80 percent of edges working, detours cut the mean time steps from about 67 to 54. The code is free in the Munich Quantum Toolkit.

Arizona teaches simple decoders to try again

Bane Vasić’s group at the University of Arizona brought three papers on decoders for qLDPC codes. The cheap decoder for these codes passes messages around a graph. It can get stuck in loops where the messages circle and never settle. Dimitris Chytas, a doctoral student, restarts a failed run by forcing the least certain points to zero and to one, and keeps up to 64 branches at each stage. On a bicycle code of length 288, the first stage cleared 93 percent of failing patterns. Their tests assume perfect measurements.

In a second talk Chytas gave each kind of link in the code graph its own damping weight, which stops the decoder swinging between two answers. Shobhit Bhatnagar took a third route. When the decoder fails, Bhatnagar opens one copy per qubit, pins that qubit’s value and keeps the lightest fix that works, and at low error rates that beat a slower standard method by about ten times.

Learning a new code at each level

Nico Meyer of Fraunhofer IIS presented for co-authors Christopher Mutschler, Dominik Seuß, Andreas Maier and Daniel Scherer, who could not attend. Concatenation nests one code inside another. Each level cuts errors sharply, and each level also multiplies the qubit count. Meyer’s team argues that every level changes the shape of the leftover noise, so every level should get a code learned for that noise.

Under one kind of noise, two learned levels hit a target with 105 times fewer physical qubits than the standard five-qubit code. Meyer called that case academic. Under uneven noise the saving was about 4.5 times, and for pure bit flips the plain three-qubit repetition code beat the learned ones. The learned codes also still lack safe logical gates.

Decoders built for qLDPC codes

The new codes need new decoders. The cheap one, belief propagation, gets stuck on them, and the usual clean-up step after it is slow and uneven. Seven talks went after speed, memory and the long tail of hard cases, and most tested on IBM’s 144-qubit gross code.

NVIDIA’s min-LLR lets one decoder handle both error types

Muyuan Li of NVIDIA showed that a small change to the standard decoder lets it fix bit and phase errors together and beat the usual split. That standard is BP-OSD, belief propagation followed by a slower clean-up that ranks bits by how confident the last round of messages was. Li’s change is small. Called min-LLR, it ranks them by the smallest likelihood ratio each bit reached over 10 rounds. Li argued that qLDPC codes win or lose their tenfold saving through this kind of co-design.

On a 72-qubit code, plain BP-OSD did far worse decoding all errors jointly, and with min-LLR the joint decoder came out ahead. It shipped the Saturday before. The same release, CUDA-Q QEC 0.8.0, runs several copies of relay belief propagation side by side on one GPU and stops at the first that settles. NVIDIA claims that cuts logical error up to 89 times on a 288-qubit code under a hard deadline of 1 to 5 milliseconds.

A Bayesian decoder that says how sure it is

Frank Mueller presented a graph neural network decoder for bicycle codes, on behalf of first author Xiangjun Mi. The usual fallback after belief propagation, ordered statistics decoding, has a cost that rises with the cube of the code size and leaves a long tail of slow decodes. Mueller’s network runs on the code’s check graph. It attaches a confidence level to every answer.

The network cut logical errors by up to 48 percent against ordered statistics decoding. It also generalises. A second scheme trains copies on several codes and merges them into one model, which still did well on a 756-qubit code it had never seen. Inference took within twice the time of belief propagation on consumer graphics cards. Mueller called that workable for the Duke ion traps the group works with, though not yet fast enough for superconducting qubits.

Belief propagation steers the Tesseract search

Francisco Garcia-Herrero of Complutense University of Madrid spoke for first author Sana Javed, with Mark Flanagan of University College Dublin and Bane Vasić. Tesseract is a decoder that gets close to the best answer by searching through sets of errors that might have tripped the checks. But its memory and time grow fast. So the team runs a damped form of belief propagation first, for at most 30 rounds, and keeps its answer when it settles.

When it stalls, its soft output reweights the search. Logical error rates stayed close to plain Tesseract, while the search nodes expanded fell by up to about 77 times and queue memory by about 30 times. Garcia-Herrero would put the damped stage on an FPGA at under a microsecond and Tesseract on a CPU in the millisecond range, both started at once to hide the fallback. Stalls came in more than half of shots, Garcia-Herrero estimated, without exact figures.

McGill matches Relay-BP with almost no multiplications

Zhengyu Cai of McGill University matched a leading decoder for IBM’s gross code while dropping about 98 percent of its multiplications, which are costly in hardware. Cai worked with Mohamad Ali Jarkas, Bokun Zhao and Warren Gross. The reference was Relay-BP. At a microsecond a round, the test of 12 rounds plus a final one leaves about 12 microseconds per window.

Cai brought back an old idea from classical codes called dithered belief propagation. When a try fails, it tries again with small random changes, and each new try starts from a blend of the last one and the first guess, so failed work is reused. It works. At a physical error rate of 0.003 the decoder made about 7 logical errors in a million, level with Relay-BP. Cai projects about 4 microseconds for an average decode, but only averages were worked out, and a few hard shots make a long tail.

Complutense fits three gross-code decoders on one FPGA

Daniel Báscones of Universidad Complutense de Madrid builds FPGAs and is new to error correction. Báscones worked with Arshpreet Singh Maan, Valentin Savin and Francisco Garcia-Herrero. Their decoder rests on GARI, a trick from Savin’s and Garcia-Herrero’s group. It rewrites the code’s graph to cut the short loops that trap belief propagation, so about 1,700 heavy rows become about 18,000 light ones that can all run at once.

Each iteration takes 596 nanoseconds. Twelve take 7.15 microseconds, inside the gross code’s window, and because the wiring lives in memory the code can change without reprogramming the chip. Three decoders fit on one AMD VCU19P, so an ensemble of 24 needs eight boards in place of 48. Splitting one decoder across several FPGAs is not viable, Báscones said.

UT Dallas shows only spare capacity cures a backlog

Ameya Bhave of the University of Texas at Dallas treated decoding as a service with queues. Bhave worked with Navnil Choudhury and Kanad Basu. Their model, DART-Q, handles each window of check data as a job with an arrival time and a deadline, and records whether it finishes on time, late or is turned away. Bhave stressed that it is a model for comparing designs and is not yet calibrated on hardware.

Overload was the test. For the 144-qubit bicycle code, adding a second decoder cut missed deadlines from 97.64 percent to 0.98. A longer queue did less good than it seemed, because it stopped jobs being dropped but left the number of answers on time unchanged. The reply time that 99 percent of jobs beat rose from 220 microseconds to 3.861 milliseconds. No single latency figure, Bhave concluded, can say whether a decoder is fit for real time.

NVIDIA teaches decoding on GPUs, from repetition codes to Ising

Mark Wolf and Justin Lietz of NVIDIA ran a two-part tutorial on fast decoders. Wolf began with a code that just keeps three copies of a bit. Lietz said the work a decoder gets through matters most, because one that falls behind builds a backlog that never stops growing. Batching helps. Running many shots at once made NVIDIA’s GPU decoder for gross codes 2.4 to 20.8 times faster. Peter Shanahan of Alice & Bob said moving design runs for an elevator code, built for cat qubits, onto GPUs cut some from two weeks to about two hours.

In the second part Lietz argued that a neural decoder can beat one that is exact for a model of the noise, because it learns the noise the device really has. The better of NVIDIA’s two open Ising pre-decoders, trained on distance-13 data, cut logical errors threefold at distance 31, and the fast one made the whole chain 2.5 times quicker than PyMatching alone. Victory Omole of Infleqtion closed with a small network on a simulated neutral-atom surface code. Told which atoms were lost, it made 2.26 percent logical errors against 2.43 percent without. Omole called it a simple example, short of a full study.

Logical qubits on real machines

The clearest way to see error correction is to run it. Two companies brought hands-on tutorials, and Quantinuum brought its best numbers to a keynote that also asked the industry to change how it keeps score. Four more teams brought data from working machines.

IQM shows how little a bare qubit can do

Daniel Bulmash, who leads education and community at IQM Quantum Computers, ran two tutorials on IQM’s 20-qubit Garnet machine. A qubit that was prepared and then measured came back wrong 0.7 percent of the time, which sounds small. At that rate, Bulmash showed, only about 15 gates keep a 90 percent chance of a right answer, while breaking RSA encryption needs about a trillion. Fifteen gates is a very short program.

Then came a three-qubit repetition code, which stores each bit as copies and takes a vote. Over 1,000 shots, 3.1 percent of the qubits flipped, yet only 0.1 percent of the shots decoded to the wrong answer. In the afternoon a four-qubit code that only detects errors did worse than a bare qubit, and Bulmash used it anyway because its check circuits are easy to see. Bulmash ended on the 500-gigabit sum that opens this guide.

QuEra counts the atom moves

Tyler Cochran and Pedro Lopes of QuEra Computing taught on Gemini, a machine that stores qubits in rubidium atoms held by laser traps. The atoms move on a grid of traps where rows and columns cannot swap places, so a badly placed circuit pays in extra moves, and every move adds a little noise. Lopes used the Steane code, in which seven atoms hold one logical qubit, giving about 10 logical qubits on the machine. Their advice was to watch the T-gate count above all.

In the hands-on half the room built logical circuits in Gemini Studio, a browser tool. A Toffoli gate filled all 10 logical qubits, needed 34 atom moves and kept just 736 of 100,000 simulated shots, because Gemini cannot yet act on a measurement mid-circuit. The machine sits at AIST in Japan. On the Thursday a QuEra speaker said the next machine, Libra, aims past 100 logical qubits at one error in a million.

Xanadu’s photonic prototype runs for a day without a stop

Priya Nadkarni of Xanadu showed Aurora, a prototype built from light that joins 84 squeezers across 24 chips with 60 fibre links held in phase. It ran for more than a day without a stop. Xanadu stores its qubits as GKP states in pulses of light, and makes its gates by measuring a large web of those pulses, all entangled. The Toronto firm wants a machine with hundreds of logical qubits and billions of gates.

On the prototype a repetition code, which keeps copies and takes a vote, was decoded in 84 nanoseconds with a latency of 1 microsecond. Xanadu calls these figures preliminary. Nadkarni also gave a rule for keeping a code’s distance against one kind of error when its graph is reshaped. It holds when a measure of how well the graph spreads, the Cheeger constant, is at least 1.

IonQ runs five codes on one chain of 40 ions

Edwin Tham of IonQ ran five different qLDPC codes on a single chain of 40 trapped barium ions, changing only software between them. Lasers can entangle any pair in the chain without moving ions, so codes with long-range checks need no new hardware. Two-qubit gates there fail about 4 times in 1,000.

For an 18-qubit code holding 4 logical qubits, the logical error per cycle was 1.95 percent for one kind of error and 1.1 percent for the other. Tham put that at 4 and 9 times better than a comparable superconducting experiment. Each cycle took 40 to 80 milliseconds. Decoding ran offline, and shots with a lost or leaked ion were thrown away, more than 60 percent of them by the sixth cycle. Tham thought one to two months of control software work would allow resets in place of discards.

Michigan State finds colour-code detection fades past distance 3

Ryan LaRose of Michigan State University tested error detection on IBM hardware. LaRose worked with Yanis Le Fur, Ethan Egger, Hong-Ye Hu, Vincent Russo and William Zeng. Detection is a lighter cousin of correction. The circuit is encoded, run and measured, and only results that land in the code space are kept, so errors shrink as the code grows, but fewer shots are kept as circuits get deeper.

A repetition-code memory on 3 to 9 qubits beat bare qubits and improved roughly exponentially with each qubit added. The colour code was harder. At distance 3 it beat the bare circuit at every depth, and at distance 5 it fell behind beyond a depth of about 20 to 30. At distance 7, on 74 physical qubits of IBM Boston, a million shots gave no valid result at all.

IQM cuts surface-code error from 20 percent to 1

William Kindel, a technical manager at IQM, said the logical error of a distance-3 surface-code memory on IQM machines fell from about 20 percent to 1 percent in about a year and a half. On the cloud device Emerald it sits just under 2 percent, with leaked shots discarded. A patch with the same median quality but a few poor qubits gave 5 percent. So IQM’s engineers have spent weeks on single bad qubits.

For the longer run IQM wants barbell codes. They are mapped from tile codes onto a layout called Constellation, where each qubit reaches its 12 nearest neighbours, and they need just one long link per check. Simulations give about six times the surface code’s encoding rate. Kindel called that plan A, though IQM’s next deliveries all use square grids.

Quantinuum asks the industry to retire quantum volume

Rajeeb Hazra, chief executive of Quantinuum, gave the Monday evening keynote in Hall G, and their theme was that buyers and investors cannot yet compare one quantum machine with another. Quantum volume, the shared score IBM put forward in 2018, needs a classical computer to check it. Past about 40 good qubits, that means renting the largest kind of supercomputer. The score also ignores time. Their answer, QUOPS, treats the machine as a black box and gives a size and a speed. A paper led by Sandia, with NVIDIA and Quantinuum, came out that day.

Hazra also read results from Helix, an error-correction design run on the Helios machine. Logical memory failed 4.6 times in 100,000 per qubit per round, with no runs thrown away. The error per logical Clifford gate, the cheaper class of gates, was 2.8 in 10,000, which Hazra called 4.2 times better than the physical gate. Apollo is still aimed at 2029. Talks with other firms on the new score are only starting.

Getting more from the surface code

Not everyone wants a new code. Three teams looked for savings inside the surface code itself, by sharing wires, by cutting helper qubits or by changing the order and mix of the checks.

Sharing control lines costs protection

Konstantinos-Nikolaos Papadopoulos of Northwestern University asked what happens when one control line serves several qubits in turn. The work was with Kaitlin Smith and Jakub Szefer. Each qubit on a superconducting chip can need up to four wires down through the fridge, and the talk cited estimates that it takes close to a million qubits to break a 2048-bit key. So sharing a line saves a lot of wire. But a qubit that waits its turn loses its state.

With two qubits per line, a distance-11 code behaved like an unshared distance-7 code. The threshold, the error rate below which bigger codes help, fell from 6.83 per thousand with no sharing to 2.80 with four qubits on a line. Asked whether a two-way switch saves any wires at all once its own control line is counted, Papadopoulos agreed that by count it does not. Papadopoulos said the switch line could be a simple digital one.

Fewer helper qubits, and a smaller best code

Shintaro Sato of NTT showed that a surface code can run with far fewer helper qubits, in work with Yasunari Suzuki of RIKEN. A standard code uses almost one helper per data qubit. Helpers cost as much as data. With two helpers the check circuit takes 2 steps, and with one it must swap along the line and takes 5.

A safer gate order stops a faulty helper from weakening the code. It costs a deeper circuit. With the device capped at 1,000 physical qubits, the largest code that fit was a poor choice, and so was the smallest. The biggest code that fits, Sato said, does not always give the fewest errors.

Princeton halves errors on damaged chips

Lakshika Rathi, a doctoral student at Princeton University, worked with Pau Escofet, Joshua Viszlai and Margaret Martonosi. Real chips have dead qubits and dead couplers. Patching around them forces some checks to take turns, and on many chips one kind of error, the phase flip, is more common than the other. Logs from six 156-qubit IBM chips over four days showed that bias reaching 2.6.

Rathi changed only the mix of check rounds. At a bias of 5 and distance 9, nine rounds of one kind for each round of the other halved the logical error. The gain grew with code size and with damage, reaching 8.4 times at distance 13 with 2 percent of parts dead. The best mix stayed within 5 percent of the lowest error across code sizes and biases, so the calibration data a lab already collects can set it patch by patch.

Testing quantum error correction decoders before the hardware exists

Most numbers in this field come from simulation. Six talks showed how far that can be trusted, and what the tools for testing look like.

Yonsei finds simulation rankings fail on hardware

Seokhyeon Son of Yonsei University put eight learned decoders to a test. Son trained each once, on a free simulator called Stim, then ran it as it was on an IonQ emulator, three IBM Heron chips and an early IBM Nighthawk. In simulation four common designs led, fixing 77 to 84 percent of errors. Two newer ones, a Graph Transformer and a Graph Mamba model, fixed fewer than 54 percent.

On hardware the order tended to reverse on every setup with a clear signal. The Graph Transformer and the Graph Mamba were the only learned decoders that did no harm anywhere, and when they ran ahead of a standard matching decoder they cut its error rate by nearly 40 percent on one IBM chip. Son’s advice was to check a decoder on the processor it will serve.

Riverlane replays a million rounds from Google

Two Riverlane engineers argued that decoding speed sets the pace of a whole fault-tolerant computer. A T gate is applied by feeding in a prepared state and measuring it, and if the result reads one a fix must follow, so nothing after it can run until that measurement has been decoded. The decoder’s delay is the machine’s clock.

Riverlane replayed Google’s million-round memory run on the Willow chip through its Deltaflow 2 decoder. The average stayed near 15 microseconds per window, against 63 that Google had reported. It did not creep up. The speakers said their decoder was simpler and less accurate than Google’s, so the two figures are not like for like, and that some windows spiked much higher.

Riverlane’s Deltaflow 2 averages 9.6 microseconds on Google’s data

Munir Hasan of Riverlane said Deltaflow 2 took 9.6 microseconds on average to answer, over a million rounds of data from a 2025 Google run that went below threshold. That is an average wait, and the replay above gave the time per window. Deltaflow 2 runs on FPGAs. Data comes in over Riverlane’s QECi link, which is public on GitHub, and a decoder that groups nearby errors does the work.

A spin-qubit researcher in the room called 10 microseconds too slow for that platform. Hasan said Riverlane is studying which parts could move to colder stages of the fridge, and that qLDPC codes do not yet fit well on an FPGA. A custom chip, Hasan said, would give roughly a fivefold gain.

QuEra’s QEC Studio

Rafael Haenel, a senior software engineer at QuEra, showed QEC Studio. It came out a few weeks before the meeting. A canvas shows the logical steps, and a double click opens the physical circuit, the noise model and the check results that sit underneath each one. It runs on a fast simulator for circuits with few T gates, and on a Microsoft tool that maps each possible error to every check it would trip.

NVIDIA warns that lost atoms break the simulators

Kyungjoo Noh of NVIDIA said lost atoms cause about half the errors in a recent Harvard result that ran the surface code on neutral atoms. Error correction can fix an atom that is there. It cannot make a new one, so without fresh atoms a code’s data qubits simply drain away.

Standard tools miss this. Stim can sample more than a million shots in under a minute for hundreds of qubits, Noh said. But it cannot skip the gates on a lost atom, so each shot needs its own circuit and sampling becomes orders of magnitude slower. Noh’s answer is a library of tens or perhaps 100 reusable blocks, each analysed once and then composed. Loss matters less for superconducting qubits, Noh added, since their defects are known when the chip is made.

Oak Ridge builds a test bed

Jack Lange of Oak Ridge National Laboratory described a test bed for error correction in real time. So far a 20-qubit IQM Radiance system called Pathfinder ran a surface code, a server stored the results, and Riverlane’s Deltaflow 2 decoded them on playback. The next step starts the replay from a real controller, so the timing matches a live loop. Lange would not name vendors or dates.

Who answers the clock

The papers left two questions open. Four panels took them up, from what builders fear to how parts from different firms should connect.

The fears of building a fault-tolerant machine

Joan Camps of Riverlane chaired a panel of seven, from IonQ, Maryland, IQM, Google, RIKEN, Aalto and Oratomic. Each one feared what their own trade makes hard. For Madelyn Cain of Oratomic it was keeping error rates low across tens of thousands of atoms, which Cain said is harder than trapping them. The IQM panellist worried about wiring up to a million qubits. The RIKEN panellist feared drift in the settings, since a decoder is only as good as its model of the errors.

The Google panellist put a 10,000-qubit machine about ten times short of commercial use. The Aalto panellist said the field knows how to decode memory but has no theory yet for decoding logic, and the Google panellist disagreed, pointing to a method called sparse blossom for lattice surgery. For trapped ions, the IonQ panellist said, the decoder has time in hand. The IonQ panellist said the company had decoded a full physics simulation on a Mac mini. Cain closed on reliability, saying a six-month job is fine until failures stretch it to three years.

Interfaces, openness and standards

Kasra Nowrouzi of QuNorth moderated seven panellists. They were Justin Lietz of NVIDIA, Janne Mäntylä of IQM, Adam Paetznick of Microsoft, Francesco Battistel of Qblox, Paul Coote of Q-CTRL, Moritz Kirste of Zurich Instruments and Munir Hasan of Riverlane. Hasan backed a standard. Hasan wants it to grow to carry slow data such as calibration drift, and said Riverlane’s QECi interface came from what four partner firms had in common.

Paetznick was wary. Paetznick noted that the floating-point standard arrived in the mid-1980s, long after computers did. Kirste said every interface their firm had agreed with Riverlane, IQM and Q-CTRL had since changed beyond recognition, a jungle Kirste did not think was bad. Lietz and Paetznick said shared terms are already settling in NVIDIA’s CUDA-Q Logical and in Microsoft’s tools, and Hasan noted that electronics standards such as HDMI charged licence fees, which this community is trying to avoid.

Industry will not pick a standard qLDPC code

Nithin Raveendran of the University of Arizona asked six company researchers where qLDPC codes sit on their roadmaps. They were Edwin Tham of IonQ, Priya Nadkarni of Xanadu, Madelyn Cain of Oratomic, Daryus Chandra of Photonic Inc., Muyuan Li of NVIDIA and Sam Smith of Iceberg Quantum. None would name a standard code. Tham gave a shared one 10 to 20 years, since an IonQ machine is not built to plug into an Oratomic one.

Each machine pays for long links in its own way. Chandra said a near photonic link costs about the same as a far one, while Smith noted that superconducting chips, fixed when made, have less room to change course than atoms, ions or spins. Smith would bet the first machine to do useful work is an LDPC one. Smith’s worry was that no test can yet judge a fast decoder at the tiny failure rates a real machine needs, and no panellist gave a decoder time from a running processor.

IBM moves its decoders from FPGAs to custom chips

Francesco Battistel of Qblox and Alexander Knapen of the University of Michigan chaired seven panellists on real-time decoding. Among them were Alexandre Bourassa of Google, Joan Camps of Riverlane and Keisuke Fujii of Kyoto University. Blake Johnson said IBM has dropped FPGAs for chips of its own. The reason is logic. Once a program starts, the kinds of decoding window grow with the square of the size of the instruction set, and that would need a few hundred FPGA images.

The panel agreed that decoders now keep up when a qubit just sits in memory. Logic is the hard part. Bourassa said a million qubits read every microsecond would send about a terabit of data a second. Johnson expected live decoding of memory in IBM’s dense codes within a year, and of a whole program within two or three years. Bourassa wanted live figures printed as standard beside offline ones.

What it means for buyers and builders

Anyone weighing an error-correction claim should first ask how long the whole loop takes on real hardware, from measuring the checks to applying the fix. Maryland’s 446 nanoseconds, with the signal looped back, was the only full superconducting loop timed here. Most other numbers came from simulation, a single board or replayed data. Son’s reversed rankings show how far simulation can mislead.

The second question is whose decoder talks to whose controller, and through what interface. Riverlane, NVIDIA and Microsoft each push shared terms, yet Kirste said even the interfaces their firm had agreed with Riverlane, IQM and Q-CTRL had since changed beyond recognition. A buyer should get the interface in writing. For the machines all this feeds, see our guide to fault-tolerant quantum computers.

Bulmash’s sum puts the problem in one line. The quickest chips already tick once a microsecond, and the decoders, controllers and interfaces that must answer them are still being argued over by firms that have not agreed a standard. Toronto never settled who answers that clock.