Imec Achieves SiMOS Qubits With EUV-Defined Nanowires

Researchers from Imec in Leuven, Belgium, and Diraq in Sydney, New South Wales, Australia, have successfully created silicon metal-oxide-semiconductor (SiMOS) qubits using extreme-ultraviolet (EUV) lithography, a technique originally developed for high-volume semiconductor manufacturing. The work demonstrates high-fidelity SiMOS spin qubits fabricated in a semiconductor pilot line, leveraging existing silicon manufacturing infrastructure rather than relying on radically different materials. Characterization of four double-dot systems reveals consistently high fidelities, with values up to 99.9 percent for SPAM, 99.8 percent for single-qubit gates, and 99.5 percent for two-qubit gates. These results establish EUV lithography as a viable manufacturing technology for quantum processors, with devices exhibiting highly reproducible exchange turn-on characteristics of 1.2 to 1.8 µeV.

SiMOS Quantum-Dot Fabrication with Extreme-Ultraviolet Lithography

A new fabrication technique leveraging existing semiconductor manufacturing processes has yielded remarkably uniform and high-fidelity silicon quantum dots, bringing scalable quantum computing closer to practical realization. This approach differs from many quantum computing efforts focused on exotic materials and fabrication methods, potentially accelerating the path toward practical quantum processors. The team’s work addresses a critical bottleneck in scaling quantum computers: the need for both nanometer-scale precision and reproducibility in qubit fabrication. While electron-beam lithography has previously achieved high performance, its serial nature limits large-scale production. EUV lithography, in contrast, exposes an entire reticle field in a single step, offering significantly higher throughput and improved overlay control. The researchers demonstrated a room-temperature gate-to-gate leakage yield, alongside sub-nanometer control of critical gate dimensions, across a full wafer, showcasing the technology’s potential for mass production.

This is particularly important given that SiMOS quantum dots generally require pitches below 10 nanometers to achieve effective electron confinement and strong exchange interaction. Gate set tomography revealed values up to 99.9 percent for SPAM, 99.8 percent for single-qubit gates, and 99.5 percent for two-qubit gates, demonstrating performance approaching the thresholds needed for fault-tolerant quantum computing. Notably, the devices exhibited highly reproducible exchange turn-on characteristics of 1.2 to 1.8 µeV, indicating a high degree of fabrication uniformity enabled by EUV patterning.

Originally developed for high-volume semiconductor manufacturing, EUV lithography is now being employed to define the nanowires forming these SiMOS qubits, a departure from the more common use of electron-beam lithography in early quantum device prototyping. The collaborative effort, detailed in recent findings, demonstrates consistently high qubit fidelities achieved through a rigorous process called gate set tomography (GST). The team characterized four double-dot systems realized within two triple-quantum-dot devices, meticulously assessing the accuracy of each quantum operation. Limitations in overlay accuracy between successive patterning layers have historically plagued e-beam lithography, hindering the scalability of larger qubit arrays. By adopting a technique already established in mainstream semiconductor manufacturing, the team hopes to accelerate the transition from prototypes to commercially viable quantum processors, aligning qubit fabrication with existing industrial infrastructure and process control capabilities.

Researchers have successfully utilized extreme-ultraviolet (EUV) lithography, a process originally designed for high-volume production of conventional microchips, to fabricate silicon metal-oxide-semiconductor (SiMOS) qubits with remarkably consistent performance. The team focused on characterizing the uniformity of exchange interactions within double quantum dots, a critical parameter for controlling qubit entanglement. Beyond simply achieving high performance in individual qubits, the work highlights the reproducibility of these results across multiple devices.

The team’s work focused on realizing triple-quantum-dot devices with a targeted pitch below 10 nanometers across a wafer, a feat previously hindered by the limitations of serial-exposure techniques like electron-beam lithography. The researchers report a room-temperature gate-to-gate leakage yield, alongside highly reproducible gate dimensions, oxide thickness, and inter-layer overlay, metrics essential for consistent qubit performance.