Inside D-Wave’s Dual-Rail Qubit Roadmap and the New Haven Bet on Logical Qubits

D-Wave bought its gate-model programme rather than building it

D-Wave announced the purchase of Quantum Circuits Inc on 7 January 2026 at a stated price of $550 million. It closed the deal on 20 January. The headline price was $300 million in D-Wave common stock and $250 million in cash, though D-Wave later recorded the fair value of what it handed over as $538.5 million. The 10,430,444 shares were struck at the $27.04 closing price on the day the deal completed.

The roots are at Yale. Quantum Circuits, usually shortened to QCI, was co-founded by the Yale physicist Rob Schoelkopf and built on patents it has licensed exclusively from Yale since November 2016. He co-invented the transmon qubit, the most widely used kind of superconducting qubit. He went on to build the dual-rail encoding that now sits at the heart of D-Wave’s gate-model work, and he is now D-Wave’s chief scientist. QCI’s own chief executive, Ray Smets, summed up the firm’s guiding idea as “correct-first”.

Schoelkopf has spent close to three decades at Yale building the base of circuit quantum electrodynamics, the field that treats superconducting circuits as artificial atoms linked to microwave light. That lineage is what D-Wave bought. D-Wave kept the QCI team in place and built around it, so the New Haven centre is where the company’s gate-model and error-correction work is based.

The deal brought more than a qubit design. In its annual report D-Wave claims to be the only company that holds all three things it thinks you need to build large, error-corrected superconducting computers on the gate model. The first is high-fidelity dual-rail qubits that detect their own errors. The second is local cryogenic control, with the control electronics in the cold next to the qubits, together with multi-chip superconducting packaging. The third is cryogenic platforms, the deep-cold systems the chips sit in, that stay up for years at a time. That third item is a claim about reliability, not physics, and it is the one that comes from the annealing side of the house.

QCI also arrived as a working business, not a lab, and it closed $2.3 million of bookings in the days just before the deal completed. D-Wave told investors it meant to make a first dual-rail system generally available during 2026. None of this was built in-house. The whole gate-model roadmap is, in effect, an inherited bet on one dual-rail qubit design and on the people who created it.

The roadmap is not a continuation of D-Wave’s annealing programme by other means. The case for the whole timeline rests on whether the dual-rail qubit design behaves the way the New Haven team says it will once the chip is large. It rests, too, on whether D-Wave’s manufacturing and control engineering can carry that design from a single logical qubit to a hundred of them inside seven years.

Annealing still pays the bills while the gate model is built

D-Wave is not dropping annealing for the gate model. In the same annual report the company calls itself the world’s first and only dual-platform quantum computing company. That is its own label, not a finding by anyone outside it. It runs the annealing and gate-model lines side by side and pitches them as partners, not rivals. The annealing side is the money-maker today, built on the Advantage and Advantage2 systems. That report also says almost 62 million jobs had been sent to Advantage2 systems and prototypes by February 2026, a figure D-Wave reads as strong demand from its customers. Its annual report says Forschungszentrum Jülich in Germany bought the Advantage system installed at its supercomputing centre. That machine had more than 5,000 qubits when the sale was announced in February 2025, and the report says it “was upgraded to an Advantage2 quantum computer throughout 2025”. Annealing is aimed at optimisation and sampling problems, and D-Wave’s longer-term plan for it talks of growing toward 100,000 qubits for jobs such as logistics and scheduling.

The second line has a different target. The gate-model programme is a separate R&D track aimed squarely at universal computing that is fault-tolerant, meaning it corrects its own errors as it runs. That is the kind of machine that could one day tackle quantum chemistry, materials simulation and other problems annealing cannot reach. D-Wave’s argument is that the same superconducting engineering, in making the chips, packaging them and controlling them in the cold, serves both lines. So on the parts of the problem that are not about the qubit itself, the gate-model effort is not starting from zero. Whether the two lines work together as well as claimed is an open question. The framing does explain how D-Wave can plausibly enter the gate-model race late and still argue that it has an engineering head start on scaling up.

A dual-rail qubit reports its own most common error

Tap the image to open it full size.

No reporter from this magazine attended D-Wave’s Investor Day on 1 June 2026. This account rests on the Investor Day deck the company filed with the SEC. That deck puts the case for the dual-rail qubit on one question, which is where errors show up and whether the hardware can see them. A dual-rail cavity qubit is not a single object like an atom, an ion, or a conventional transmon. It is built from two superconducting cavities joined by a coupler, with a transmon and measurement hardware attached, and all of it sits at the base of a dilution refrigerator.

The unit of quantum information is a single photon at microwave frequency. If the photon sits in the first cavity the qubit reads as zero, if it sits in the second it reads as one, and it can sit in any superposition of the two. Control is done with microwave pulses. The state is changed by sending microwave signals to the coupler for exactly timed spells, which moves the photon between cavities or puts it in a chosen superposition.

Photon loss leaves a third state the hardware can detect

The design pays off when something goes wrong. In a dual-rail qubit the dominant failure mode is photon loss, where the photon is absorbed or otherwise disappears. That loss leaves the qubit in a distinctive third state that is neither zero nor one. The state can be detected with high accuracy at the level of a single qubit, and D-Wave’s claim is that this catches roughly 90% of errors as they occur. It converts ordinary noise, which most architectures cannot localise, into a flagged erasure, meaning an error whose location and timing are known.

An erasure is far cheaper to fix than a hidden error. Conventional error correction has to spend qubits and steps first finding out that an error happened somewhere and then working out where, but an erasure announces itself. That changes the arithmetic of the code. Codes built for noise that is mostly erasures can take a much higher error rate before they break down, so the same physical hardware does more correcting work per qubit.

The company is pointed about the comparison. It argues that this kind of built-in erasure flag, on each single qubit, is much harder to get from the transmons that IBM and Google rely on. It is not unique to the dual-rail qubit, though. Trapped-ion and neutral-atom groups have shown their own erasure conversion, turning errors into flagged erasures, and D-Wave’s version is a very clean case, with photon loss flagged all the time as it happens.

The strongest evidence for any of this came on 5 August 2026, when the New Haven group published its dual-rail qubit entangling gate in Nature. The gate runs in about 500 nanoseconds and leaves an error rate below 0.1% once the detected errors have been taken out. That is where the 99.9% figure D-Wave quotes comes from. About 0.5% of gates end in a flagged erasure. Those are counted apart from the 99.9%, and inside an error-correcting code an erasure is repaired rather than thrown away, because the code knows where it happened. So the 99.9% measures the errors the hardware cannot see, not the raw success rate of every gate tried.

The same paper reports an asymmetry between the two kinds of error. Bit-flip errors are bounded at the level of a few parts per million, and erasures and dephasing run three to four times higher on the control qubit than on the target qubit. That lopsidedness is exactly what codes designed for biased noise are built to exploit. The design has speed on its side as well, since superconducting circuits cycle far faster than atoms or ions, and D-Wave puts the gap at 100 to 1,000 times. Error correction is a race between finding errors and accumulating them, so cycle speed counts.

The DR figures are physical qubits, not logical ones

D-Wave’s processors carry DR prefixes that denote dual-rail qubit counts, and the numbers are widely misread. The DR figures are physical qubit counts, not logical ones. One chart carries the whole argument. The error-scaling chart in the deck D-Wave filed with its June 2026 Investor Day runs along an axis of quantum-error-correction code distance. It marks d=3, d=5, d=7 and d=9 against 17, 49, 97 and 181 physical qubits, and across that axis it plots two lines, one for Lambda of 2 and one for Lambda of 10.

DR-181 is one logical qubit, not 181

Each early system is in effect a single logical qubit built at a rising code distance. The higher the distance, the more physical qubits it takes and the lower its error rate. D-Wave names only three processors, DR-17, DR-49 and DR-181, for 2026, 2027 and 2028, and the 97-qubit distance-seven point sits on the error-suppression curve rather than being a dated product.

That reframes the published milestones, drawn from the roadmap D-Wave announced on 1 June 2026. The provenance of the table is mixed. The year, the qubit count and the error-reduction factor are D-Wave’s, while the pairing of each system with a code distance comes from the error-scaling chart in the same deck. The logical-qubit column for the early rows is this magazine’s reading rather than a number the company prints.

None of the early entries is a count of logical qubits. DR-181 is not 181 logical qubits. It is a single, high-quality logical qubit assembled from 181 physical dual-rail qubits, and it is the blueprint demonstration that the architecture can produce a logical qubit good enough to build on. The actual logical-qubit counts arrive only in the later milestones, with ten in 2030 and a hundred in 2032. The genuine sequence is a single demonstrated logical qubit around 2028, then ten of them two years later, then a hundred two years after that. The last of those is the one capable of running more than a million operations.

D-Wave's 8 September 2026 release on its CHIPS award describes that machine as a 10,000-qubit system designed to enable 100 logical qubits. That is 100 physical qubits per logical qubit, fewer than the 181 in DR-181. On the rotated surface code, 100 qubits reaches only distance seven, so D-Wave would need a lower distance than DR-181 or a leaner code. It has not said which.

The roadmap needs a tenfold error cut per step, where Google got about two

Tap the image to open it full size.

Quantum error correction has a standard shorthand that makes the whole chart legible, written as [[n, k, d]]. The double brackets mark it as a quantum code rather than a classical one. The first number, n, is how many physical qubits the code uses. The second, k, is how many logical qubits it protects. The third, d, is the code distance, meaning the smallest number of physical errors that can corrupt the logical information without being detected. Distance is the one that matters. A distance-d code can correct up to (d−1)/2 errors, so a higher distance buys stronger protection, and the logical error rate falls sharply as d climbs.

Every one of D-Wave’s early systems has k equal to one. Put in this notation, the roadmap points are roughly [[17, 1, 3]], [[49, 1, 5]], [[97, 1, 7]] and [[181, 1, 9]]. That way of writing it is ours, not D-Wave’s, since the company gives physical qubit counts and code distances, not bracket notation. Those n values track the rotated surface code closely.

A rotated code is the standard yardstick here, because it needs 2d²-1 physical qubits to protect a single logical qubit, which is exactly why d=3, 5 and 7 give 17, 49 and 97. The last point does not fit exactly. A bare rotated code at d=9 would be 161, and DR-181 is twenty qubits larger, though D-Wave has not published a breakdown of what that difference is spent on.

So DR-181 is the [[181, 1, 9]] milestone, namely one logical qubit, distance 9, built from 181 physical dual-rail qubits. The error is easy to make. Reading the 181 as a k value rather than an n value is the most common misunderstanding of the roadmap, and it inflates the achievement by more than two orders of magnitude.

The error-rate numbers carry the rest of the story, and they connect directly to the metric the chart is built around, which is Lambda. The physical error rate is around one in a thousand, consistent with the 99.9% two-qubit fidelity. Three figures anchor the curve. The published suppression factors are two times at d=3, twenty times at d=5 and two thousand times at d=9.

Those are not arbitrary. Each step of the distance by two multiplies the suppression by Lambda, and a Lambda of ten applied at each step gives 2, then 20, then 200, then 2,000. D-Wave publishes the 2, 20 and 2,000 figures; the 200 at distance seven is the interpolation that closes the sequence rather than a number the company prints. Google’s Willow chip reported a Lambda of 2.14, where each step roughly halves the error. Reaching a two-thousand-fold suppression at that rate would take many more distance steps, and therefore hundreds or low thousands of physical qubits per logical qubit.

That gap is the whole efficiency claim. The erasure detection in the dual-rail qubit is what is meant to buy the higher Lambda. Flagging lost photons as erasures raises the code’s error threshold, the most error it can stand, and in effect stretches its distance, so the same number of physical qubits does more correcting work.

Wiring, not the qubit, is the roadmap’s hardest problem

The roadmap’s hardest stretch is not the physics of a single logical qubit but the jump from there to many. In 2028 a single distance-9 logical qubit takes 181 physical qubits, and 100 logical qubits in 2032 will take about 10,000 by D-Wave’s own figure. That jump runs straight into the bottleneck that limits every superconducting machine, which is wiring. Each qubit normally needs its own control and readout lines run down into a dilution refrigerator, and the count of lines gets out of hand well before qubits reach the tens of thousands. This is why qubit-count roadmaps so often stall.

D-Wave’s answer to wiring comes from its annealing chips

D-Wave’s answer is the second of the three items on its list, local cryogenic control paired with multi-chip superconducting packaging. On-chip control moves much of the signal-making down into the cold next to the qubits, and that cuts the number of wires running from room temperature into the fridge by orders of magnitude. Packaging does the other half. It lets modules be built and linked together, rather than etched onto one ever-larger die, or slab of silicon. The company puts a number on what this already buys it on the annealing side. Its annealing designs, it told the Investor Day, make 100,000 control signals in the cold from fewer than 300 lines coming in from outside.

Here the dual-platform argument earns its keep. D-Wave has spent years building this kind of superconducting control for its annealing chips, which already run at qubit counts that no gate-model machine comes near. Trevor Lanting, D-Wave’s chief development officer, presented this part of the Investor Day with Schoelkopf. One slide in that deck reads, “We demonstrated scalable cryogenic control of gate model qubits with no loss of fidelity”. That is a claim on D-Wave’s own slide, not a peer-reviewed result.

Error flags reach programmers first through a simulator, not hardware

The usual gate-model toolbox is single-qubit gates, two-qubit entangling gates and measurements. On top of it D-Wave is adding what it calls error-aware programming, and this is where the dual-rail design pays off in software, not just in physics. The programme adds three things to that toolbox. The first is the error-aware measurement. It returns a zero or a one, plus an extra flag that says whether that qubit has had an error, which turns the erasure detection into data you can use.

The second is mid-circuit error detection. It can be placed anywhere in a circuit and reports whether a qubit has had an error without collapsing its state. So a program can keep running while the programmer learns where errors are piling up. The third is real-time classical-quantum control flow, which lets classical arithmetic and true-or-false Boolean logic run in nanoseconds and feed back into the quantum program as it runs.

D-Wave argues the value goes beyond error correction. Mid-circuit detection gives a steady stream of data on how each qubit changes through a run, and that by-product can be mined for insight, including early trials of machine learning. The company is also putting this in front of developers before the hardware is ready.

It announced a gate-model simulator built for error-aware programming on 18 June 2026. It handles up to 21 qubits and works inside Ocean, D-Wave’s coding kit. That release promised access through the Leap cloud in September 2026. Leap already runs the annealing machines. Once the simulator is on general release, users will have one place to work on both kinds of machine, and existing customers should find it easy to try gate-model code.

What arrived on 1 October 2026 was a beta, not a general release. D-Wave's own release says the programme “offers select customers early access to the simulator in advance of its general availability”. No general release has been announced since. Those taking part include BBVA, FirstQFM, Florida Atlantic University and the Jülich Supercomputing Centre, who all reach it through Leap, and the same release says the real machines are still to come.

FirstQFM's plan comes from its chief executive, Vish Ramakrishnan, quoted in that release. The firm will apply its “proprietary foundation models for quantum computing” to explore how “detected errors, mid-circuit error signals and real-time control” can make quantum calculations more reliable.

D-Wave trails on logical-qubit count and bets on depth instead

D-Wave’s standing against the field has two halves. On the raw count of logical qubits it has some catching up to do, since several competitors already have working machines or nearer-dated roadmaps. That is not the contest D-Wave has entered. Its roadmap is built around needing far fewer physical qubits for each logical qubit rather than around posting the biggest number first.

D-Wave is not the first or the fastest to logical qubits, and the codes its rivals use explain how they pushed their counts up so quickly. Quantinuum leans on the all-to-all connectivity of trapped ions to run light error-detecting codes. The codes are cheap by design. Those codes buy a great many logical qubits for very few physical ones, by accepting that some runs will be discarded rather than repaired.

Its Helios page markets 50 logical qubits on 98 fully-connected physical qubits, a ratio close to two to one. The paper behind it runs tests carrying between 48 and 94 logical qubits. It uses the Iceberg code, which detects errors, and a two-level concatenated version of it, a code nested inside itself, that reaches distance four. Those tests include preparing a GHZ state, an entangled state in which every qubit shares a single outcome, and simulating a 3D model of magnetism. The abstract says plainly that the results rest on postselection, meaning runs are thrown away when the code flags an error, and it calls the rates reasonable without printing one. It adds that nesting the code to a higher distance cuts those discards. That is a different claim. It shows computing on encoded qubits with bad runs thrown out, not a machine that repairs itself while it runs. Until September 2026 the best-known published case of repeated, real-time error correction on a single logical qubit, with no runs thrown away, came from Google. Quantinuum’s 2 September 2026 preprint reports repeated quantum error correction on Helios, and it has not yet been through peer review.

IBM has moved off the surface code entirely to bivariate-bicycle qLDPC codes, where each qubit is checked by a few distant partners rather than only by its neighbours on the chip. Its “gross” code, published in Nature in 2024, is [[144, 12, 12]], meaning 144 data qubits carry twelve logical qubits at distance twelve. Counting the syndrome-extraction ancillas, the helper qubits that read out errors, roughly doubles the physical total. So the real cost per logical qubit is about twice what the bracket suggests. The density is the payoff. Packing twelve logical qubits into one block is still far more efficient than a k-equals-one surface code. What it asks in return is the long-range links that qLDPC codes need and that a flat chip does not easily provide.

Google has shown below-threshold error correction with its Willow chip, meaning the errors shrink as the code grows, and that is the result that produced the Lambda of 2.14 D-Wave measures itself against. It names a long-lived logical qubit as its next goal. The company that has gone furthest in the lab is QuEra, spun out of Harvard and MIT. It has already done in a physics lab some of what D-Wave is promising for the next decade.

A team led by Harvard, with QuEra among its members, ran algorithms on 48 logical qubits as far back as 2023, using low-distance codes and heavy post-selection. That was only the start. The same group went further in Nature in November 2025. It set out a fault-tolerant design for universal quantum computing, built on arrays of up to 448 neutral atoms. It used high-rate [[16, 6, 4]] codes, which store six logical qubits in sixteen physical ones at distance four.

Most of the wider field still runs on plans, not results

The wider field is more crowded still, and most of it runs on published plans, not published results. IonQ, also a trapped-ion company, has a roadmap that reaches into the millions of physical qubits by 2030. The IonQ plan is an outlier. Those numbers sit far beyond what the rest of the field says it will build, and IonQ’s own annual report calls them only a published roadmap whose milestones may not be met. Microsoft is chasing topological qubits, which are meant to resist errors by their very nature, through its Majorana programme. It published a single-shot parity measurement on indium-arsenide and aluminium devices in Nature in February 2025. What that result means is disputed. A preprint by the physicist Henry Legg argues that the test Microsoft used earlier to pick out topological devices cannot be trusted. Microsoft is also working with Atom Computing, which uses neutral atoms, on logical qubits for the near term. PsiQuantum is betting that it can build fault-tolerant machines of a million qubits that run on light later in the decade.

Microsoft’s logical qubits ran on other firms’ hardware

Microsoft sits in the picture in yet another way. It has shown logical qubits as a software layer running on partners’ hardware, not on chips of its own. Its qubit-virtualization system has made entangled logical qubits on Quantinuum’s trapped ions and on Atom Computing’s neutral atoms in a run of demonstrations in 2024. Each time a partner supplied the physical machine.

Those are real results, but the logical qubits ran on Quantinuum’s and Atom’s machines, while Microsoft wrote the code that fixed errors. Its own hardware bet is the Majorana work above.

On raw count, then, D-Wave is some way back. What makes that gap less telling than it first appears is what those competing logical-qubit counts are actually made of.

Why a bare qubit count misleads

A bare count comparison is misleading, though, and the reason is code distance. The Harvard and QuEra logical qubits and Quantinuum’s fifty are all low-distance, with the 2023 atom work resting on distance-two codes and the 2025 design on distance four. Low-distance logical qubits are shallow. The limit shows up in long circuits. They can be made, entangled and measured, but they pick up errors too fast to run the long circuits a real application needs. The headline results lean on throwing runs away, not on repairing them as they go.

D-Wave is doing the opposite. Its DR-181 target is a single logical qubit at distance nine with errors cut 2,000-fold below the physical rate. That would be a deep, durable logical qubit built to last through long runs. Setting the field’s dozens of distance-two and distance-four logical qubits against D-Wave’s one distance-nine qubit is comparing breadth with depth. D-Wave’s count of physical qubits per logical qubit only looks poor because it is quoting a far higher distance, where the cost of any logical qubit rises steeply whatever the type of qubit.

An efficiency bet, not a head start

What D-Wave is actually claiming, then, is an efficiency and scaling argument rather than a head-start argument, and the competition splits along three axes. The first is how many logical qubits exist today, where the neutral-atom and trapped-ion platforms are far ahead. The second is how many physical qubits each logical qubit costs at a given distance, where IBM’s qLDPC blocks and the light ion and atom codes look cheap. The third is how fast the logical error rate falls as the distance and the system grow. The third axis is D-Wave’s. That is the axis D-Wave is betting on, because its Lambda-of-ten dual-rail qubit claim, if it holds, is the steepest in the field.

The saving would be large. If that scaling is real, the company would reach deep, low-error logical qubits with something closer to a hundred physical qubits each. A standard superconducting approach using the surface code might need around a thousand, so the cost of every later milestone changes. D-Wave’s case against its rivals is not that it reaches logical qubits first or builds the most of them. It is that each logical qubit should cost far fewer physical qubits, and that is the lever that decides whether a fault-tolerant machine is affordable to build at all.

D-Wave’s real rivals are the cat-qubit teams, not IBM or Google

D-Wave says that error detection on each single qubit is something no other type of qubit offers, and that framing needs a caveat. The dual-rail qubit belongs to a known family of hardware-efficient, or bosonic, error correction whose whole premise is the same. The idea across this family is to build the qubit so that its main error is either held down in the hardware or made plain to detect. That cuts the number of physical qubits each logical qubit needs. The other camp does the opposite. That is the surface-code and qLDPC camp of IBM and Google, which uses large numbers of generic qubits and leans on clever codes to do the work.

The cat-qubit teams making the same bet

The closest cousins to the dual-rail qubit are the cat-qubit teams, whose qubits hold two opposed microwave waves at once so that bit flips almost never happen. They are making the same bet with different hardware. Amazon published its Ocelot work in Nature in February 2025 under the title hardware-efficient quantum error correction via concatenated bosonic qubits. Ocelot is a memory for a logical qubit. It holds down bit-flip errors in the hardware itself and then catches the phase flips that remain with an outer code. What unites Amazon, Alice & Bob and D-Wave is not any one of these methods but the ratio they are chasing. That ratio is a logical qubit costing far fewer physical qubits than the thousand or so a plain surface code would need. D-Wave's annual report claims up to an order of magnitude fewer physical qubits per logical qubit, which puts its own figure near a hundred rather than in the tens.

The French company Alice & Bob reported in Nature in May 2024 that it had held a cat qubit with bit-flip times exceeding ten seconds. The mechanisms are not the same, since the dual-rail qubit flags photon loss as an erasure while cat qubits suppress bit flips and detect phase flips. The strategy is shared, namely trading hardware sophistication for far lower overhead than a surface code. D-Wave is making a particularly clean version of this bet rather than a unique one. The real contest is closer to home. Its real fight for the title of most overhead-efficient superconducting path is with AWS and Alice & Bob, not with IBM or Google.

Cash and the first CHIPS tranche last to mid-2030, short of the 2032 roadmap

D-Wave laid out this roadmap on 1 June 2026 at its first Investor Day, a session badged “The D-Wave Difference” and run by five named executives. The framing was aimed at investors as much as at physicists. The pitch, made by chief executive Alan Baratz, is that the company already has a real annealing business that earns revenue, and is now adding a distinct, credible path to gate-model fault tolerance. On that view it can tell a dual-platform growth story that rivals working only on the gate model cannot. The deck also carried a slide about money rather than physics.

It disclosed a letter of intent for a $100 million investment from the United States government. The deck calls this proposed funding under the CHIPS and Science Act, and says D-Wave would issue $100 million of its shares to the Department of Commerce in exchange. That deal has since been signed. D-Wave entered the award agreement on 4 September 2026 and issued the Department 7,095,721 shares four days later. The money comes in tranches, about $53.6 million first and the rest tied to milestones such as building and benchmarking processor prototypes. None of it is in the June-quarter figures below, and D-Wave's own filing warns that the timing and amount remain uncertain.

D-Wave spends about eighteen times its revenue

The finances under the story are still early and uneven. D-Wave reported first-quarter 2026 revenue of $2.9 million against far stronger bookings of $33.4 million. Most of that came from one $20 million system sale to Florida Atlantic University. The second-quarter figures published on 6 August 2026 put revenue at $3.1 million and quarterly bookings at $2.1 million, which lifted first-half bookings to $35.5 million. First-half revenue fell 67% to $5.9 million. The fall comes from a $13.7 million system sale in the same half of 2025, not from a collapse in demand.

The quarter carried a net loss of $48.0 million against operating expenses of $55.0 million, so the company is now spending roughly eighteen times its quarterly revenue. It has the cash to do so for now. At 30 June 2026 it held $296.6 million in cash and equivalents plus $249.6 million in marketable securities, or $546.2 million in total. That is down from $588.4 million three months earlier and from $819.3 million a year before. More than 90% of the year-on-year decline went to the cash half of the Quantum Circuits purchase.

Operations used $73.5 million of cash in the first half, a figure that excludes the $5.5 million spent on equipment, and at that rate the June balance lasts about 3.7 years, into early 2030. The first CHIPS tranche of $53.6 million lifts the total to $599.8 million and the runway to about 4.1 years, or mid-2030. The full $100 million would add roughly eight months to the June figure. The CHIPS milestones, which include installing tools and fabricating prototype processors, point to more spending, not less. The roadmap runs to 2032, so D-Wave would still need to raise money, grow revenue or slow spending to see it through.

One listing detail has changed since the Investor Day. D-Wave voluntarily transferred its listing from the New York Stock Exchange to Nasdaq, and the shares began trading there on 27 July 2026 under the unchanged ticker QBTS. The roadmap runs to 2032, so most of what it promises sits years beyond the next set of results. DR-17 and DR-49 are the first two points at which any of it can be checked against hardware rather than against a slide.

DR-49 must beat DR-17 about tenfold or each logical qubit costs ten times more

None of this is settled yet. D-Wave does not pretend that it is. The gate-model programme is still research and development rather than a product, and the roadmap runs all the way to 2032. The headline Lambda-of-ten figure is a target rather than a result shown on a large device, in a field where timelines have a long history of slipping.

It is also true that rivals have logical qubits running today while D-Wave does not, which is the catching up the company has to do. The bet is falsifiable on a short clock. The June roadmap dates DR-17 to 2026 and DR-49 to 2027, and the 6 August results repeated both dates. The cleanest test is the ratio between the two machines. Lambda is the factor by which the logical error rate falls from one code distance to the next, so DR-17’s rate divided by DR-49’s reads it directly. A ratio near ten would support the bet, and a ratio near two would refute it. If DR-17 meets its target of errors twice below the physical rate, a Lambda of ten puts DR-49 about twentyfold below.

A ratio near two would match the Lambda of 2.14 that Google measured. This assumes the standard surface code, with 2d²-1 physical qubits per logical qubit and errors falling by a factor of Lambda each time the distance rises by two. At a Lambda of two, a 2,000-fold cut needs about distance 23, or roughly 1,000 physical qubits per logical qubit. That is about ten times the 100 per logical qubit in D-Wave's 10,000-qubit plan, so the same machine would hold fewer than ten logical qubits instead of 100.

One caveat sits in the background. It is about annealing, not the gate model. In May 2026, researchers at the Flatiron Institute’s Center for Computational Quantum Physics published work in Science. It suggested that a classical tensor-network algorithm could redo parts of the problem behind D-Wave’s headline annealing-supremacy claim, which was published in Science in 2025. Tensor networks model quantum systems on ordinary computers. The paper does not overturn the annealing case, but it is a fair reminder that bold claims in this field get tested hard and fast. In the end the gate-model roadmap will be judged on results shown in the lab, not on slides.

What D-Wave bought in New Haven is a route, not a win. It is not a promise to reach logical qubits first or to build the most of them, but a route to making each logical qubit from far fewer physical ones. The first hard evidence arrives with DR-49 in 2027. A logical error rate about ten times below DR-17’s, rather than about two, is the test the whole bet has to pass.

Frequently asked questions