The easiest way to understand qLDPC codes is to start with the letters. LDPC stands for low-density parity check, and the low density is the whole idea: every error check touches only a handful of qubits, and every qubit is watched by only a handful of checks, no matter how large the code grows. That sparseness keeps the checking circuitry shallow and the error rate of the checks themselves under control, which is what makes the family practical at all.

The reason qLDPC codes have moved from a theorists’ curiosity to the centrepiece of IBM’s fault-tolerance roadmap is arithmetic rather than elegance. The reigning champion of quantum error correction, the surface code, spends thousands of physical qubits to protect a dozen logical ones, and that overhead is the single largest line item in every plan for a useful machine. The best qLDPC codes buy the same protection roughly ten times more cheaply, and when every qubit is an engineering project in its own right, a tenfold saving reshapes what a useful machine costs to build.

This guide walks through what the codes are, where they came from, what IBM’s celebrated gross code actually claims, which machines have now run qLDPC codes for real, and the two honest catches, wiring and logic, that decide whether the family takes over. It completes our error-correction series alongside the surface code guide.

What qLDPC actually means

qLDPC codes are quantum error correction codes that keep every parity check small and every qubit lightly monitored, which lets one block protect many logical qubits at once. Formally, quantum LDPC codes are stabilizer codes in which the number of qubits in each check, and the number of checks watching each qubit, are both capped by a constant however big the code gets. Codes are described by the shorthand [[n, k, d]], meaning n physical qubits protecting k logical qubits with distance d, the number of errors it takes to silently corrupt the encoded information, and the ratio k over n is the code’s rate, the fraction of the hardware doing useful work.

Here the vocabulary plays a small joke on newcomers. By the strict definition the surface code is itself a qLDPC code, since its checks touch at most four qubits, but it encodes exactly one logical qubit per patch, so its rate collapses towards zero as it grows. In practice, when the industry says qLDPC codes it means the high-rate members of the family, the codes that pack many logical qubits into one block while keeping the checks sparse, and that is the usage this guide follows. The community’s catalogue of qLDPC codes records hundreds of constructions in the family.

A code family with a past life

The classical half of the story is one of the great second acts in engineering. Robert Gallager invented low-density parity-check codes at MIT, in a 1960 doctoral thesis published as a paper in 1962, and the world’s computers were far too weak to run them, so they were shelved and forgotten for over thirty years. MacKay and Neal rediscovered them in 1996, found they performed near the theoretical Shannon limit, and the second act began.

Today the classical versions are quietly everywhere. Satellite television adopted them in 2003 after LDPC beat rival turbo-code proposals in open competition, 10-gigabit Ethernet runs on them, they are optional in older Wi-Fi and widely used in modern versions, and the 5G data channel in modern phones is protected by an LDPC code. The quantum versions inherit that engineering pedigree along with the name, and part of the field’s confidence is precisely that the classical cousins have four decades of deployment behind them.

Why the surface code needs a successor

The surface code earned its dominance honestly, with the highest known tolerance for hardware noise and checks that only ever involve neighbouring qubits on a flat grid. The price is written in its parameters. A distance-d patch spends roughly two d squared physical qubits to protect a single logical qubit, so useful distances cost hundreds of qubits each, and a dozen well-protected logical qubits costs roughly three thousand. Worse, the inefficiency is a law rather than a design flaw: a 2010 result known as the Bravyi-Poulin-Terhal bound proves that any code wired only between neighbours on a 2D chip must obey this kind of scaling.

That theorem is the gap every qLDPC effort exploits. Escape the flat grid, allow a few connections that reach across the chip, and the bound no longer applies, which is the trade the high-rate codes make. Theorists led by Daniel Gottesman had argued as early as 2013 that constant-rate sparse codes could shrink fault-tolerance overhead to a constant factor, saving thousands of physical qubits in a single design decision, if only good enough codes could be found. Finding them took another decade.

The overhead argument for qLDPC codes in one picture. IBM’s gross code protects 12 logical qubits with 288 physical qubits, where surface-code patches of equal protection need nearly 3,000. Diagram by Quantum Zeitgeist.

The theory breakthroughs

The modern family tree starts in 2009, when Tillich and Zémor showed how to weave two classical codes into a quantum one, the hypergraph product, giving the first constant-rate qLDPC codes, though their distance grew only with the square root of the block size. For a decade that square root looked like a wall. Then, in a single astonishing stretch between September and December 2020, three separate groups broke it with fibre bundle, lifted product and balanced product constructions, each pushing distance further than the last.

The finish line came in November 2021, when Panteleev and Kalachev posted a construction achieving the theoretical maximum, constant rate and distance growing in step with the code itself, settling a conjecture the field had chased for twenty years. A simpler independent route, the quantum Tanner codes of Leverrier and Zémor, followed within months. These asymptotic champions are not the codes anyone plans to build, but they proved the ceiling was real, and the practical codes now on roadmaps are their engineering-friendly descendants.

Seventeen years from first construction to breakeven. The theory of qLDPC codes was settled in 2021; the hardware years began when IBM put the gross code on its roadmap. Diagram by Quantum Zeitgeist.

IBM and the gross code

The construction that dragged qLDPC codes onto corporate slides is IBM’s bivariate bicycle code with parameters [[144, 12, 12]], nicknamed the gross code because 144 is a dozen dozen. Published in Nature in March 2024, the design stores 12 logical qubits in 144 data qubits plus 144 check qubits, 288 in all, and IBM’s simulations showed those 12 logical qubits surviving nearly a million error-checking cycles at realistic noise, protection that would cost nearly 3,000 physical qubits in surface-code form. The paper puts the encoding-overhead saving at better than ten to one, with a noise threshold, the physical error rate below which enlarging the code starts to help, of 0.7 per cent, on par with the surface code.

Two caveats belong beside the headline. The Nature result is architecture and simulation rather than a hardware demonstration, and the design demands connections no ordinary chip has, with each qubit wired to six others across two separate coupler layers, some links reaching right across the processor.

That demand now drives IBM’s hardware roadmap: the Loon chip, unveiled in November 2025, carries the long-range couplers the code requires, the Kookaburra module due in 2026 is designed to store and process encoded information, and the fault-tolerant Starling machine promised for 2029 targets 200 logical qubits and a hundred million operations, with the 2,000-logical-qubit Blue Jay pencilled in for 2033 and beyond. The company describes the qLDPC route as cutting error-correction overhead by roughly 90 per cent, and it has bet its entire fault-tolerance programme on it.

The first machines to run one

Hardware results arrived in a rush across 2025 and 2026. The first bivariate bicycle code ever run on real qubits came not from IBM but from a Tsinghua-led team in China, whose 32-qubit Kunlun superconducting processor, fitted with the necessary long-range couplers, ran an [[18, 4, 4]] version in May 2025 and published in Nature Physics in January 2026; the code corrected errors but its logical qubits did not yet outlive the hardware’s raw ones. That milestone, breakeven, fell in June 2026 to IonQ, which ran nine different error-correcting codes across three families, five of them qLDPC, on a chain of 40 trapped ions and reported logical lifetimes comparable to, and in one case marginally exceeding, the best physical qubit in the machine.

The neutral-atom camp attacked from the high-rate direction. The Harvard, MIT and QuEra collaboration’s landmark Nature paper, published in January 2026, ran up to 96 logical qubits simultaneously by tiling sixteen blocks of a compact [[16, 6, 4]] code across 448 atoms, results tracked on our logical qubit leaderboard. A follow-up QuEra study in April 2026 simulated codes packing 580 logical qubits into 1,152 physical ones, a rate above one half. Keep two qualifiers attached: the small tiled codes are high-rate blocks rather than members of a scalable qLDPC family, and the 580-qubit result is simulation, not hardware. Even so, all three platforms reported their first qLDPC results within thirteen months of one another.

The wiring problem

The catch that kept qLDPC codes theoretical for so long is that sparse checks are not local checks. The same mathematics that lets the codes beat the surface code obliges some of their checks to reach across the machine, and follow-up theory proved the requirement cannot be engineered away: beat the 2D bound and long-range wiring comes with the territory. Which platform pays that price most gracefully has become one of the sharpest dividing lines in quantum hardware.

Machines whose qubits move, or whose qubits are light, pay almost nothing. Neutral-atom arrays physically rearrange their atoms between checking rounds, a capability a 2024 Nature Physics blueprint turned into a constant-overhead architecture, trapped-ion chains enjoy effective all-to-all connectivity, which is what let IonQ run nine codes without touching its hardware, and photonically networked designs treat long range as a founding assumption. Fixed superconducting grids have it hardest, and the responses define the camp: IBM built new coupler hardware, while Finland’s IQM designed barbell codes for its high-connectivity Constellation lattice in June 2026, reporting fewer than 30 data qubits per logical qubit in simulation, which its press materials round to an eightfold saving over the surface code.

Decoding on a deadline

Every error-correction cycle ends with a classical computer reading the check results and deciding where the errors sit, and here the surface code has a running start. Its errors pair up neatly, so a matching algorithm decodes it in well under a microsecond per round. General qLDPC codes offer no such neat pairing, and their workhorse decoder, belief propagation patched by an expensive linear-algebra step, has historically been orders of magnitude slower, an awkward fact for superconducting machines that finish a checking round in about a microsecond.

The gap is closing fast enough to be its own storyline. Riverlane’s ambiguity clustering decoder reported gross-code decoding roughly 27 times faster than the standard method at matched accuracy, and IBM’s answer, a lighter algorithm called Relay-BP running on an off-the-shelf FPGA, demonstrated real-time decoding of the gross code at under 480 nanoseconds per round in November 2025, a year ahead of the company’s own schedule. Real-time qLDPC decoding, long listed among the family’s disqualifying weaknesses, now looks like an engineering problem in the ordinary, solvable sense.

The missing piece, logic

Storing logical qubits cheaply is not the same as computing with them, and computation is where the surface code still holds the high ground. Surface-code patches perform logic through lattice surgery, a mature, well-understood choreography of merging and splitting, while a dense qLDPC block has no equally natural way to reach the qubits packed inside it. The compactness that makes the codes cheap is precisely what obstructs the logic: twelve logical qubits share one tangle of physical qubits, there is no separate patch to slide around, and a clumsy operation on any part of the block risks disturbing every logical qubit stored in it at once.

For a while the sceptics’ summary was that qLDPC codes made excellent memories and poor processors. The last two years have eroded that summary from several directions at once. Generalised surgery schemes now perform logical measurements on qLDPC blocks, an IBM refinement showed every Clifford operation on the gross code with about a hundred extra ancilla qubits, bridging constructions connect qLDPC memories to other codes, and a 2025 theoretical result even found family members with transversal non-Clifford gates, attacking the last layer of the problem. The state of play as of mid-2026 is that nobody has yet demonstrated full logical computation inside a scalable high-rate qLDPC code on hardware. Every vendor’s roadmap requires it within the next few years.

Who is betting on qLDPC

The commercial map splits three ways. IBM is the maximalist, with its entire fault-tolerant roadmap from Loon through Starling to Blue Jay resting on bivariate bicycle codes.

A second tier has adopted the family as its differentiator: IonQ with its breakeven demonstration, IQM with tile and barbell codes for superconducting lattices, Photonic Inc, whose SHYPS codes, published in Nature Communications in May 2026, are designed for efficient logic across photonically linked modules, and Alice and Bob, whose architecture lays a classical LDPC code over its cat qubits, a cousin of the full quantum construction, to reach around a hundred logical qubits from 758 cats in its published design. The error-correction specialists, led by decoder maker Riverlane, sell to all of them.

The most instructive entry on the map is the abstention. Google, whose Willow result remains the flagship demonstration of below-threshold error correction, is staying with the surface code and its colour-code relatives, betting that the incumbent’s maturity in logic and decoding outweighs the newcomers’ economy. That split, overhead against maturity, is the genuine state of the argument, and our earlier coverage of the qLDPC design shift traces how quickly the balance has been moving. Both camps agree on the destination, a machine whose logical qubits are cheap enough to count in the thousands, and disagree only about the cheapest road.