Tier IV will share AI chip designs for self-driving cars

TIER IV has joined the Japan Science and Technology Agency’s Next-Generation Edge AI Semiconductor Research and Development Program to open-source designs for AI chips intended for Level 4 autonomous driving, a specific level of autonomy requiring continuous AI model operation in real-world conditions. Professor Yoshihiro Kawahara of The University of Tokyo’s Graduate School of Engineering leads a research team focused on “use-case-driven, functionally differentiated physical AI chip design” within the JST program. TIER IV intends to develop the chip’s logic design for efficient autonomous driving AI processing and to open-source the design assets and associated toolchain, aiming to establish an open ecosystem for semiconductor manufacturers.

JST Program Advances Software-Defined SoC for Level 4 Autonomy

Level 4 autonomous driving demands substantially more from onboard computing than current systems typically deliver; existing graphics processing units, while powerful, present a significant power consumption bottleneck for deployment in battery-powered vehicles. The initiative aims to move beyond simply accelerating AI models to creating an adaptable, transparent, and verifiable computing foundation for self-driving cars.

The resulting chip will be evaluated with Autoware, the leading open-source software for autonomous driving, allowing for comprehensive system-level testing. A key innovation lies in the adoption of the Tensor Operator Set Architecture (TOSA), a standardized intermediate representation that decouples AI models from the underlying hardware.

This allows for greater flexibility, as changes to AI model architectures or computational methods can be implemented primarily through software updates, reducing the need for costly and time-consuming chip redesigns. Shinpei Kato, founder and CEO of TIER IV, said, “Advances in AI have been accelerated by powerful computing platforms, including GPUs, which have enabled rapid progress across the industry.” He continued, “As Level 4 autonomous driving moves toward broader deployment, we believe the next step is to complement these platforms with computing architectures designed for real-world and real-time requirements.” The team will prioritize verifiability, establishing mechanisms to mathematically verify the numerical consistency of AI model transformations before execution on the chip. By fostering an open ecosystem, TIER IV hopes to accelerate the commercialization of SoCs for Level 4 autonomous driving and establish a more reliable foundation for the future of autonomous vehicles.