Altera and Riverlane have validated Riverlane’s Quantum Error Correction Interface (QECi) on Altera Agilex 7 FPGAs, offering developers a platform for evaluating quantum error correction data movement and integration. The partnership uses Altera’s high-speed transceivers to enable fast, low-latency data exchange for connecting quantum control and error-correction systems. “Quantum error correction requires tremendous parallel processing, high-speed connectivity and predictable timing as systems scale,” said Farhad Shafai, vice president of business solutions at Altera. Riverlane has published the QECi design example on GitHub, providing an open-source resource for the quantum computing community.
Agilex 7 FPGA Validates Riverlane’s Low-Latency QECi Interface
This validation moves beyond theoretical quantum error correction to an FPGA-based implementation, offering developers a tangible starting point for integration and assessment. Riverlane’s QECi design example, now publicly available on GitHub, standardizes data exchange between quantum control systems and error-correction hardware, an important step toward interoperability as quantum architectures evolve. These transceivers deliver the necessary bandwidth for real-time quantum error correction, a capability previously limited by slower data transfer rates.
The Agilex 7’s programmable fabric also allows developers to tailor processing capabilities to the specific demands of qubit control, readout, and QEC data paths, offering a flexible architecture for complex quantum systems. Riverlane is committed to building a practical quantum error correction ecosystem, and this collaboration with Altera is a key part of that strategy.
The company, founded in 2016 and headquartered in Cambridge, United Kingdom, has rapidly become a leader in the field, raising over $125 million to develop its Deltaflow software platform. This platform, coupled with the recently launched qeciphy, a robust physical layer implementation for FPGA-to-FPGA communication, provides a complete solution for real-time QEC. “Riverlane is focused on making quantum error correction practical across the full quantum-computing ecosystem,” said Marco Ghibaudi, vice president of engineering at Riverlane.
Riverlane’s roadmap, published earlier this year, details how its technology could potentially accelerate the development of utility-scale quantum computing by three to five years, and this validation on Altera hardware represents a concrete step toward that goal, the company says. The company’s recent partnerships with Rigetti Computing and Oxford Quantum Circuits, integrating Deltaflow 2 into existing quantum systems, further demonstrate its commitment to real-world deployment and interoperability. Riverlane experts will be available at IEEE Quantum Week 2026 to discuss the QECi solution and its potential to advance quantum error correction.
Quantum error correction requires tremendous parallel processing, high-speed connectivity and predictable timing as systems scale.
Farhad Shafai, vice president of business solutions at Altera
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