Zi-Han Chen and colleagues at University of Science and Technology of China propose the Hierarchical Logical Processor (HLP), a system concatenating a high-rate quantum code with the rotated surface code to improve encoding efficiency and reduce the need for complex, non-local couplings. The HLP limits long-range connectivity to once every several rounds of error correction, using ‘shuttle buses’ to efficiently link quantum patches and enable highly parallel logical measurements. Simulations demonstrate that this HLP achieves three to four times higher qubit efficiency than the standard rotated surface code at a physical error rate of 10⁻³, alongside a key reduction in physical qubit overhead and faster error-correction cycles.

Novel architecture boosts qubit efficiency and reduces error correction overhead

At a physical error rate of 10⁻³, the Hierarchical Logical Processor (HLP) achieves three to four times higher qubit efficiency than the standard rotated surface code, representing a substantial leap in quantum computation performance. Previously, implementing high-rate quantum low-density parity-check (qLDPC) codes necessitated complex, non-local couplings which limited scalability and increased error. These non-local couplings, requiring direct interaction between distant qubits, introduce significant physical error and implementation complexity, hindering the development of large-scale, fault-tolerant quantum computers. The HLP circumvents this issue with a new architecture that concatenates a high-rate quantum code with the rotated surface code, reducing the need for problematic connections and enabling more efficient encoding. The rotated surface code, while robust, often requires many physical qubits to encode a single logical qubit, creating a substantial overhead. By combining it with a high-rate code, the HLP aims to mitigate this limitation.

This design allows for more efficient encoding and addresses a key limitation of previous approaches. A reduction of 100–200 units in physical qubit overhead per logical qubit and a shortening of the logical error-correction cycle time by a factor of 20-30 are achieved by the HLP, paving the way for more practical quantum computers. The concept of qubit overhead is crucial; it refers to the number of physical qubits required to reliably encode a single logical qubit, which is protected from errors. Reducing this overhead is paramount for building quantum computers with sufficient scale to tackle complex problems. The HLP’s architecture achieves this by strategically organising qubits into ‘patches’ and utilising the ‘shuttle buses’ for efficient communication. These ‘shuttle buses’ act as dedicated pathways for transferring quantum information, minimising the need for direct, long-range interactions. Sixteen concurrent ‘shuttle buses’ extract stabilisers in parallel, allowing the HLP to operate close to its full potential distance, and the architecture exhibits logical error rate decay approximately twice as fast as the standard rotated surface code. Stabilisers are measurements used to detect and correct errors in quantum states. Parallel extraction significantly speeds up the error correction process. Performance is particularly notable at higher distances, indicating improved scalability and robustness against errors as the system size increases. Distance, in this context, refers to the code distance, a measure of the code’s ability to correct errors; a higher distance implies greater error correction capability.

Enhanced qubit efficiency and reduced overhead pave the way for scalable quantum computation

Researchers at University of Science and Technology of China have unveiled a new quantum computer architecture, the Hierarchical Logical Processor, designed to tackle the persistent challenge of error correction in increasingly complex systems. Quantum computers are inherently susceptible to errors due to the delicate nature of quantum states and their interaction with the environment. Error correction is therefore essential for building reliable quantum computers, but it comes at a significant cost in terms of qubit resources and computational time. The team’s approach improves qubit efficiency and reduces the physical overhead compared to yoked surface codes. Yoked surface codes represent another approach to quantum error correction, but they often suffer from limitations in connectivity and scalability. Circuit-level simulations, however, underpin this work, representing a simplification of the realities of building and operating quantum hardware. These simulations allow researchers to model the performance of the HLP architecture without the complexities of physical implementation, providing valuable insights into its potential benefits.

Further research will focus on validating these results with physical implementations, and addressing questions regarding optimisation for diverse quantum platforms; this reliance on simulations introduces a degree of uncertainty regarding practical scalability. Building and operating quantum hardware is a challenging undertaking, and the performance of a simulated architecture may differ from that of a physical device due to factors such as noise, imperfections in qubit control, and limitations in connectivity. Investigating the HLP’s performance on different quantum platforms, such as superconducting qubits, trapped ions, and photonic systems, is crucial for determining its versatility and adaptability. The new design strategically combines a high-rate quantum code with the rotated surface code, and introduces ‘shuttle buses’, dedicated communication channels within the processor, to streamline error correction. The high-rate code provides efficient encoding, while the rotated surface code offers robust error correction capabilities. By reducing reliance on complex connections between qubits and enabling more efficient data transfer within the system, the Hierarchical Logical Processor represents a vital architectural step towards practical fault-tolerant quantum computation. Fault-tolerant quantum computation refers to the ability to perform quantum computations reliably, even in the presence of errors, by employing sophisticated error correction techniques. The HLP’s architecture offers a promising pathway towards achieving this goal, potentially unlocking the full potential of quantum computing for solving complex scientific and technological challenges.

The research demonstrated that the Hierarchical Logical Processor (HLP) achieves improved qubit efficiency compared to the standard rotated surface code, attaining a 3-4 times higher performance at a physical error rate of 10^-3. This matters because reducing the need for complex connections between qubits simplifies the architecture required for fault-tolerant quantum computation. The HLP uses a combination of a high-rate quantum code and ‘shuttle buses’ to streamline error correction and data transfer. Researchers intend to validate these simulation results with physical implementations and explore optimisation for various quantum platforms.

👉 More information
🗞 Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses
🧠 ArXiv: https://arxiv.org/abs/2606.22594

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