IBM stacks silicon wafers for a denser, faster chip

IBM is developing a new approach to chip design with its nanostack architecture, achieving nearly 100 billion transistors on a chip the size of a fingernail. This innovation builds transistors upward, rather than outward, overcoming the spatial limits of traditional scaling and changing how semiconductors are manufactured. Initial projections suggest nanostack chips will consume 70% less energy and run 50% faster than existing 2nm node technologies, benefiting applications from AI to mobile devices.

IBM’s Nanostack Architecture: Breaking 2D Scaling Limits

The nanostack architecture reconfigures transistor arrangement, allowing for the stacking of nanosheets and a departure from traditional two-dimensional scaling limitations. IBM’s approach fundamentally alters how transistors are built, moving beyond the established X and Y axes to incorporate the Z axis for increased density and performance.

This shift represents a significant change in logic technology scaling, with projections indicating the potential to extend these advancements to 2040. The architecture’s flexibility allows for the strategic layering of transistor types; Tenko Yamashita, senior manager for advanced logic pathfinding technology at IBM Research, explained, “You can put n-type on top of p-type, or p-type on top of n-type, depending on what kind of channel material and process you want.” Power delivery within nanostack chips also diverges from conventional methods, using the backside of the wafer instead of the front where signals are typically routed.

This adjustment streamlines the manufacturing process and improves overall yield, as fewer processing steps are required to achieve the desired line definition. “And that improves your yield because you’re not processing over and over again to try to get the line,” said Bonilla, highlighting the efficiency gains.

ASML, a key player in lithography technology, is actively collaborating with IBM on this development; Christophe Fouquet, president and CEO of ASML, stated, “ASML is proud to be engaged early in the development of nanostack architecture, which relies on the higher resolution and tighter process control enabled by High NA EUV technology.” Advanced lithography, with its improved patterning and reduced complexity, is helping to realize the potential of this new architecture. The move to nanostacks fundamentally alters the question of transistor density, shifting the focus from maximizing the number of transistors within a two-dimensional space to using three-dimensional stacking.

IBM’s innovation isn’t solely about adding more transistors, but about reimagining the very structure of the chip itself. Rich Wise, vice president for the Aether product line at Lam Research, acknowledged this progress, saying, “We congratulate our partner IBM on its new nanostack architecture, which reflects real progress in 3D logic scaling.” Lam Research’s Aether dry resist technology is critical to achieving the atomic-scale precision required for these advanced device architectures.

“This achievement builds on our collaborative innovations in advanced dry EUV photoresists. Advanced device architectures demand atomic-scale precision – and Lam’s Aether dry resist provides it, enabling chipmakers to achieve the full resolution potential of High NA EUV,” Wise added. Beyond the architectural changes, IBM Research scientists are actively exploring new materials to further enhance the performance of both n- and p-type transistors within the nanostack.

Even as the industry approaches the physical limits of scaling, with 7 angstroms nearing the size of a few atoms, optimizing materials at the nanoscale offers opportunities for continued improvement. The collaboration between IBM and Tokyo Electron (TEL) has been important in driving these advancements.

Toshiki Kawai, president and CEO at TEL, emphasized the importance of this partnership, stating, “Nanostack represents the latest chapter in the long history of IBM and TEL collaboration, helping enable new eras in logic devices.” Looking ahead, continued innovation in lithography, etching and bonding processes, alongside related technologies, will be essential for the continued development and evolution of nanostack technology.

“As we look ahead, continued innovation in lithography, etch, and bonding, together with related enabling technologies, through close collaboration between IBM and TEL — will be key to advancing this technology and shaping its evolution over the coming decade,” Kawai said.

The development of nanostack architecture is not simply a technical feat. It’s a demonstration of the power of collaborative innovation and a strategic response to the challenges of maintaining Moore’s Law. Yamashita noted, “But the innovations in materials and tools have really helped spur the development of these technologies. It’s amazing when you think about it.” The team anticipates that these advancements will allow them to continue pushing the boundaries of chip technology for years to come, even as traditional scaling methods reach their limits.

Sub-18nm Back End of Line Drives Nanostack Density

A sub-18-nanometer back end of line pitch, critical for interconnecting transistors, unlocks the density gains achievable with IBM’s nanostack architecture. This extremely tight pitch allows for greater transistor density per unit area, a key factor in extending logic technology scaling beyond traditional limits. The resulting architecture reimagines how transistors are arranged, moving beyond simply shrinking their size to stacking them vertically. This shift in design philosophy is projected to extend logic technology scaling to 2040, addressing concerns that transistor scaling was nearing a physical barrier.

“We always talked about, even 10, 15 years ago, hitting a brick wall, that at some point transistor scaling would stop just because we couldn’t get there,” explained an IBM researcher. The nanostack approach bypasses this limitation by creating a three-dimensional structure, effectively increasing the available space for transistors without increasing the chip’s footprint.

This is achieved through a dual backside power delivery system, which improves chip density and allows for more efficient power distribution. The benefits extend beyond simply packing more transistors onto a chip. Nanostack designs deliver both energy savings and faster computation. Performance gains include a 40% increase in on-chip memory, according to Yamashita, alongside the previously reported 70% reduction in energy consumption and 50% speedup compared to existing 2nm node technologies.

This combination of efficiency and performance is particularly important for demanding applications like artificial intelligence, where both processing speed and power consumption are critical factors. Innovations in materials science and manufacturing processes are essential to realizing the potential of nanostack technology. “Nanostack is happening today because of some key technologies that were not available in the past,” said Huiming Bu, vice president of IBM Semiconductors Global R&D.

These include thin dielectric bonding with thermally conductive material, which improves heat transfer in increasingly dense circuits, and advanced 3D metrology and inspection techniques for quality control. The team is also focused on developing electronic design automation tools compatible with these new 3D chip designs, ensuring a smooth transition for chip designers. The development of nanostack technology also necessitates improvements in chip backside and bevel manufacturing processes.

These processes are critical for creating the necessary structures for stacking and interconnecting the nanosheets. ASML’s role in enabling nanostack architecture is also significant, with the company’s High NA EUV technology providing the necessary resolution and process control. “Advanced lithography’s improved patterning and reduced process complexity is being used to realize the potential of exciting new innovations, and IBM’s nanostack technology is a prime example,” Fouquet said.

The industry is now entering a new era of chip design, one where the focus is shifting from two-dimensional scaling to three-dimensional stacking. “We are running out of tricks to be able to put them closer and closer together, given their different sets of materials,” said a researcher, highlighting the limitations of traditional scaling methods. By embracing a vertical architecture, IBM is not only overcoming these limitations but also clearing the way for a new generation of high-performance, energy-efficient microchips.

Nanostack Technology Projects 70% Energy Reduction & 50% Speedup

Achieving a 40% increase in on-chip memory capacity alongside projected energy and speed improvements, the architecture uses optimized transistor placement and power delivery. By stacking n-type and p-type transistors sequentially, IBM’s nanostack design bypasses limitations inherent in traditional side-by-side arrangements, allowing for material selection tailored to each transistor type. Moving power delivery to the backside of the wafer, a technique known as dual backside power delivery or backside power distribution network, further enhances chip density and performance.

This shift, rather than delivering signal from the front, streamlines the power network and reduces congestion on the chip’s surface. The ability to consistently produce these stacked structures relies heavily on advanced lithography and etching techniques. These include advancements in thin dielectric bonding with thermally conductive materials to improve heat dissipation in the increasingly confined spaces within the chip.

Finally, electronic design automation tools must be adapted to accommodate these new three-dimensional chip designs. The team is actively addressing these challenges to ensure the semiconductor industry is prepared to scale nanostack technology efficiently. The potential impact of nanostack technology extends beyond performance metrics. Similarly, the anticipated 50% speedup over 2nm chips will accelerate demanding tasks such as artificial intelligence model training and inference. This combination of efficiency and performance positions nanostack technology as a critical component in the future of computing.

The innovations in materials and tools that have enabled nanostack architecture are, according to the research team, truly remarkable. This sentiment highlights the collaborative effort required to overcome the complex challenges inherent in building chips with this level of density and sophistication, and suggests a promising future for continued innovation in semiconductor technology.

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