Taiyo Holdings achieved a 700-nanometer critical dimension in its first three-layer redistribution layer formation on 12-inch wafers, a key step toward finer-pitch wiring for advanced semiconductor packaging, the company says. The company presented these findings on its FPIM Series material at the IEEE ESTC 2026 conference in Helsinki, Finland, in collaboration with imec. According to imec, dual damascene processes will become essential for wiring pitches of 1.6 micrometers or less, positioning Taiyo Holdings’ material as potentially important for the technology. These results represent an achievement in interconnect technology.
FPIM Series Enables 700-nm CD Three-Layer RDL Formation
This precision, enabled by the newly developed FPIM Series material, signifies a move toward finer-pitch wiring for advanced semiconductor packaging. The company’s work, co-authored with imec, focused on a dual damascene process, a technique increasingly vital as wiring dimensions shrink. The FPIM Series is a negative-tone i-line photosensitive insulating material specifically designed for these dual damascene processes, addressing a growing need within the semiconductor industry.
The achievement of 700-nm CD highlights the significance of Taiyo Holdings’ advancement, according to the company. This achievement builds upon earlier collaborative work; in November 2025, Taiyo Holdings and imec jointly presented findings on forming a three-layer RDL structure with a 1.6-micrometer CD on 12-inch wafers, demonstrating a clear progression toward even finer resolutions. Initial evaluations confirmed favorable electrical characteristics for the 700-nm CD metal 1 layer, specifically regarding leakage current and resistance, indicating the material’s potential for high-performance applications.
Through joint research with imec, the material was confirmed to offer both excellent electrical characteristics and high resolution, while also proving suitable for use with the CMP process, a semiconductor manufacturing technique used to planarize wafer surfaces. The collaborative research began in October 2022, demonstrating a sustained commitment to pushing the boundaries of interconnect technology. This work confirms the material’s suitability for advanced packaging, potentially enabling submicron-class RDL design rules.
Taiyo Holdings intends to continue refining the process, aiming for RDL formation with a CD of 500 nanometers or less on wafers, alongside ongoing verification of long-term performance and reliability. The company has already begun shipping small-volume samples of the material for research and development purposes, starting in 2025, suggesting a pathway toward commercialization.
Taiyo Holdings aims to contribute to the growth of the semiconductor packaging field, particularly in enabling improvements in the performance of artificial intelligence semiconductors, the firm reports. The company’s presentation at the IEEE ESTC 2026, held in Helsinki, Finland, detailed these findings and outlined future research directions, signaling a specific timeline for this technological advancement and its potential impact on the industry.
