Researchers have created a new computing platform using reconfigurable molybdenum disulfide dual-gate transistors with a ferroelectric hafnium zirconium oxide layer, unifying logic, synaptic, and neuronal functions within a single device. The work addresses a core problem in neuromorphic systems: excessive energy consumption caused by processing irrelevant data; the team’s architecture co-designs front-end logic and spiking neural networks to suppress this “task-irrelevant information at the front-end” before spike generation. This platform uses hardware to select task-directed inputs, reshaping the scale of downstream networks and reducing unnecessary neuronal activation.
Molybdenum Disulfide Dual-Gate Transistors Enable SNN-in-Logic
The transistors, built from dual-gate molybdenum disulfide, allow for dynamic configuration between high-performance logic and neuromorphic operation, achieving a subthreshold slope of 63.8 mV dec−1 and an on/off current ratio exceeding 109. This performance facilitates accurate, logic-based data filtering and adaptable synaptic behavior essential for spiking neural network computation. The architecture directly addresses inefficiencies inherent in conventional neuromorphic systems, where all input features are often processed indiscriminately, leading to excessive neuronal activation and substantial energy consumption.
A key innovation lies in the ability to suppress “task-irrelevant information at the front-end” before the computationally intensive spiking process begins, a strategy that promises significant energy savings. The entire process, researchers note, can be integrated at the back end of line during manufacturing.
These reconfigurable field-effect transistors, or RFETs, utilize monolayer molybdenum disulfide transistors paired with ferroelectric hafnium zirconium oxide layers to achieve their versatility. The researchers report near-ideal switching characteristics with the described parameters, supporting both volatile and non-volatile transitions that support adaptable spiking neural network computation. This adaptability allows the system to dynamically adjust its processing based on the specific task, further optimizing energy efficiency and performance.
Published: 14 September 2026. The work builds on prior efforts to improve the performance and stability of molybdenum disulfide transistors through dielectric engineering, as detailed in research published in 2022. The team’s approach offers a pathway towards building more powerful and energy-efficient neuromorphic computing systems capable of tackling complex, high-dimensional data processing tasks.
Front-End Logic Reshapes Spiking Neural Network Scale
This integration allows the system to isolate spatial requirements for different tasks; for example, the platform can differentiate between the broad area needed for vehicle recognition and the focused detail required for license-plate identification. This logic-level filtering directly defines the input dimensionality of the spiking network, determining the number of synaptic and neuronal tiles activated for each task and enabling energy-efficient, task-adaptive inference. Reconfigurable field-effect transistors are central to this approach, built from dual-gate molybdenum disulfide devices incorporating a ferroelectric hafnium zirconium oxide layer.
Fabricated using back-end-of-line-compatible processes, the transistors are organized into reconfigurable tiles whose roles can be reassigned across tasks, reshaping the effective scale of downstream spiking neural networks. Device-calibrated simulations of a large-scale spiking neural network, configured as input-1,024-512-128-1, quantify the inference-energy scaling behavior of this new architecture, using per-tile energy costs extracted under conservative operating conditions.
The platform’s capabilities were validated using the Modified National Institute of Standards and Technology and Street View House Numbers benchmarks, assessing its system-level energy scaling with task-dependent input complexity during real-world multitask inference. By suppressing task-irrelevant information before spike generation, the system reduces unnecessary computation and improves energy efficiency.
“By contrast, the proposed SNN-in-logic architecture enables task-dependent spatial selection through front-end logic,” the researchers write, “isolating either the coarse spatial extent required for vehicle recognition or the compact, high-detail region needed for license-plate recognition.” All codes used in the research are available from the corresponding authors upon request.
Ferroelectric Hafnium Zirconium Oxide Layer for Reconfigurable Function
The ability to dynamically configure the transistor represents a departure from conventional approaches that treat logic and neuromorphic functions as separate processes. Detailed analysis of the material composition was conducted using a Thermo Scientific Super-X energy-dispersive X-ray spectroscopy system, equipped with four independent silicon drift detectors, to verify the successful formation of the ferroelectric layer. The resulting reconfigurable logic circuit allows for task-configurable gating that preserves greyscale information in target regions while blocking irrelevant pixels at the hardware level.
Analogue pixel intensities are applied at the transistor drain, while dual-gate logic inputs selectively enable or suppress signal propagation, demonstrating the platform’s ability to perform task-directed input selection. Voltage transfer characteristics of the inverter, measured under dual-gate mode, show the input voltage applied simultaneously to both back and top gates, influencing signal propagation.
Logic-Driven Input Selection Reduces Neuronal Activation
Constraining input to task-relevant regions of a 3,072-pixel traffic scene reduced total inference energy, according to findings published on September 14, 2026. This energy reduction stems from a new computing architecture where front-end logic and spiking neural networks are co-designed to selectively process incoming data at the hardware level, minimizing unnecessary neuronal activation before signal propagation begins.
The architecture’s ability to discriminate input signals with varying temporal strengths relies on task-dependent integration behavior, demonstrated through consistent device performance across ten transistors revealing a reproducible firing window of 23-26 µA. A representative threshold current of 25 µA was selected to balance robustness and activation efficiency throughout the device population, ensuring reliable operation.
This selective activation is further amplified when processing higher resolution images; while conventional spiking neural networks experience a sharp rise in energy consumption as input resolution increases to 216,216-pixel colour images, the new system mitigates this growth through logic-based input selection. Analysis of tile activation statistics revealed that confining synaptic computation to task-relevant spatial regions significantly reduces the number of active tiles, dropping from 880,579 in an unpruned scenario to 269,771 for vehicle recognition and 94,096 for license-plate recognition.
For license-plate recognition, the system achieved an energy consumption of only 0.066 Joules, further demonstrating the efficiency gains of this approach. This adaptability is crucial for real-world applications requiring versatile and energy-efficient processing of high-dimensional perceptual data, a long-standing challenge in modern electronics.
Back-End-of-Line Fabrication of Reconfigurable Tiles
The fabrication of these reconfigurable tiles relies on a process compatible with existing semiconductor manufacturing techniques, a critical factor for scalability and eventual integration into larger systems. Unlike many emerging neuromorphic designs requiring entirely new fabrication facilities, these molybdenum disulfide dual-gate transistors are built using back-end-of-line processes, allowing them to be incorporated into current chip designs with minimal disruption to existing workflows. This adaptability significantly lowers the barrier to adoption for manufacturers already invested in conventional silicon fabrication.
Each functional tile comprises a fixed 16×16 array of reconfigurable devices, enabling a flexible hardware integration and scalable system architecture. These tiles are not static; their operational role, logic, neuron, or synapse, is programmed according to the demands of the specific task being performed. This dynamic allocation allows for front-end logic pruning, effectively reshaping the scale of downstream spiking neural networks and suppressing unnecessary hardware activation.
The result is a system that avoids redundant neuronal activation and minimizes energy consumption by focusing computational resources only where they are needed. The architecture’s ability to dynamically allocate tiles is demonstrated in simulations of complex visual inference, including a real-world traffic intersection scenario involving both car recognition and license-plate recognition. Detailed circuit implementations and simulation results, available in supplementary materials, showcase the tile’s mode-dependent operation and performance characteristics. By performing spatial pruning before the spiking dynamics begin, logic-based input selection directly reshapes the effective input space of the spiking neural network.
DG-RFET Configuration Supports Logic and Neuromorphic Primitives
The molybdenum disulfide dual-gate transistor’s ability to function as logic, synapse, and neuron within a single device establishes a new level of hardware unification for spiking neural networks. This versatility stems from the device’s configuration, allowing signal-controlled operation and tight integration of front-end logic with neuromorphic computation without functional interference. The core of this functionality lies in a ferroelectric hafnium zirconium oxide layer, enabling non-volatile synaptic plasticity and charge confinement within an aluminum oxide interlayer to ensure data retention, a critical feature for sustained learning.
Prolonged negative voltage pulses reverse polarization, modulating voltage drop and returning trapped electrons to the transistor layer, further refining reconfigurability. Paired-pulse facilitation experiments confirm the volatile behavior essential for neuronal operations, demonstrating how preceding stimuli influence subsequent responses.
Applying successive positive pulses with intervals ranging from 0.01 to 1 millisecond revealed an exponential decay in response following a 3.0-volt programming pulse, indicating temporal potentiation and mirroring biological neuron behavior. Synaptic operations also exhibit notable plasticity, with improved linearity and symmetry in both long-term potentiation and long-term depression processes achieved using fixed-width pulses and demonstrating excellent cycle-to-cycle stability. These characteristics are quantified in supplementary materials, further validating the device’s neuron-like temporal integration capabilities.
This integrated functionality translates to significant advantages in circuit design and performance. The DG-RFET achieves complex logic gates, such as inverters, AND, and OR gates, with a minimal component count.
“Compared with conventional neuromorphic approaches based on fixed network topologies or algorithmic sparsification, our approach offers a scalable and efficient hardware framework for task-adaptive neuromorphic computing,” the researchers state, particularly suited for complex sensing scenarios where input relevance shifts during inference. The device’s near-ideal switching characteristics, high on-state current, and robust switching behavior further contribute to a compact and efficient hardware solution for scalable data filtering prior to neuromorphic processing.
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