A ten-year gap typically separates the sophistication of chips worked with by the author from those powering everyday computers, demanding extreme reliability from space-based silicon. Steven Truitt, who began his engineering career working on satellite checkout and operations, recently bridged that divide by completing a full chip design, from initial specification to physical layout, for the first time.
Utilizing Microsoft Discovery, Truitt walked through the entire process, a project he describes as a way to He partnered with Professors Liu and Wu to demonstrate AI assistance in chip design workflows at DAC 2026, building a RISC-V core with an AI accelerator array.
From Aerospace Background to RISC-V Core Design with Discovery
Satellite systems demand exceptional chip reliability, a necessity achieved through the use of sapphire substrates to mitigate cosmic ray bombardment and ensure long-term operational stability. This exotic material choice underscores the extreme conditions faced by space-based electronics, a stark contrast to the silicon found in everyday computing devices. The resulting design targets a low-powered embedded device, demonstrating a practical application of the workflow.
Truitt’s project began with a high-level specification from Professors Liu and Wu, outlining a RISC-V core integrated with a matrix multiplication accelerator; he then translated this into logical C code before expanding it into high-level synthesis (HLS) C to assemble the logical blocks. This progressive approach to detail mirrors established engineering practices, but the integration of AI assistance through Microsoft Discovery was important to the process, the company says.
According to Professor Nan, “The experience highlighted an interesting difference between getting a design to work and optimizing it for different use cases,” emphasizing the value of connecting AI coding agents with electronic design automation tools. These tools expose design bottlenecks and inform iterative hardware optimization, building intuition about critical design elements and focusing optimization efforts.
Microsoft Quantum, the company behind Discovery, pursues topological qubits based on Majorana zero modes, a technology still under development as of April 2026; their Majorana 1 chip, announced in February 2025, represents a first hardware implementation of a tetron qubit device utilizing these modes. The chip employs a topoconductor, an indium arsenide-aluminium heterostructure, which creates Majorana zero modes, and error correction remains a challenge. Microsoft has invested internally in quantum computing since its founding in 1997, and in January 2025 launched a $200,000 research program to support academic work on fault-tolerant, measurement-based topological quantum computing.
This investment, alongside the opening of a new quantum computing lab in Denmark in November 2025, demonstrates a commitment to scalable quantum technologies and the Q# programming language. Prior to undertaking this project, Truitt possessed only an abstract understanding of chip design; however, he ultimately produced a physical-layout design for further development and potential fabrication. The completed layout represents a significant learning experience for an aerospace engineer expanding his skillset into the realm of silicon.
The experience highlighted an interesting difference between getting a design to work and optimizing it for different use cases. It is important to connect coding agents like Discovery with electronic design automation (EDA) tools, so that synthesis and implementation reports can expose design bottlenecks and inform the next iteration of hardware optimization.
HLS C and Verilog RTL Implementation via Microsoft Discovery
The translation of a logical design into register-transfer level (RTL) code proved an important step in a recent chip design project, evoking parallels to parametric design in spacecraft engineering for the engineer undertaking it. Utilizing Verilog, the project detailed the implementation of fundamental logical devices, AND, XOR, and others, necessary for the chip’s functionality, a process that allowed for exploration of the space between abstract logic and physical modelling. This approach facilitated a complete cycle, moving from initial specifications to a physical layout using OpenROAD, a progression previously inaccessible to the engineer despite a career spent working with completed chips.
Synthesis and implementation reports generated by these tools, she explained, provide insights that inform iterative hardware optimization, fostering an intuitive understanding of critical design elements and where to focus improvement efforts. The project’s success extends beyond a functional chip layout; it represents a shift in mindset for the engineer, who now incorporates an “always learning mindset” into their work. Inspired by the Latin phrase “Ad Astra”, traditionally used to wish spacecraft success, they added “Semper Disco” to reflect this iterative nature.
Microsoft Quantum’s underlying technology, focused on topological qubits via Majorana zero modes, supports this exploration, though error correction remains a challenge as of April 2026, according to the company. The company also partners with Atom Computing and QuNorth on Magne, targeting a quantum computer by late 2026 with more than 1,200 physical qubits, positioned as the first commercially available system of its kind. Microsoft targets code signing for quantum resilience by 2029, and its roadmap envisions a quantum supercomputer with one million physical qubits and verified fault-tolerant operation, potentially revolutionizing fields like chemistry, materials science, and pharmaceuticals.
AI-Assisted Vibe-Coding Bridges Design and EDA Workflows
The project used the OpenROAD open Physical Design Kit and SKY130 process node, providing an accessible alternative to proprietary foundry tools and enabling open-source development of the chip layout. This approach lowered the barrier to entry for experimentation and collaboration, allowing for wider participation in the design process. The translation of logical specifications into a physical layout was significantly accelerated by Microsoft Discovery, a platform that organized the project and managed numerous details otherwise requiring substantial time and resources.
Verilog, used to describe the logical devices, allowed for a parametric design space reminiscent of spacecraft design, bridging the gap between abstract logic and a concrete physical model, the firm reports. This step, previously a significant hurdle for those without specialized expertise, became a hands-on learning experience, demonstrating the potential of AI assistance to democratize chip design. The resulting physical-layout design represents an achievement for someone new to the field.
The company’s Azure Quantum cloud platform further facilitates access to quantum resources and tools for researchers and developers. Microsoft’s partnership with Atom Computing, established in 2024, integrates neutral-atom hardware into Azure Quantum.
This collaboration, alongside work with QuNorth on the Magne computer targeting more than 1,200 physical qubits by late 2026, demonstrates a multi-faceted approach to building scalable quantum systems, the company states. The development of the topoconductor, an indium arsenide-aluminium heterostructure, remains central to Microsoft’s pursuit of topological qubits, a technology not yet fully verified as of April 2026.
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