NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor

NextSilicon is expanding beyond acceleration, announcing plans to productize its Arbel RISC-V core into 64-core and 128-core enterprise processors designed for artificial intelligence and high-performance computing. Originally conceived as the control processor within NextSilicon’s Maverick-2 accelerator platform, handling serial logic and data movement, the Arbel core has evolved into a standalone solution validated by key industry players. “Arbel exists because NextSilicon needed a core that could keep up with the rest of the system,” the company stated, highlighting the core’s initial proving ground within a live deployment. Customer and partner evaluations, including feedback from HPC program leads and AI infrastructure architects, are now directly shaping the architecture of the 64-core production processor, targeting a 3.4 GHz operating frequency and a move to a more advanced process node.

Arbel Core Validated for AI and HPC Infrastructure

This validation follows an October preview and expands upon technical details, signaling a significant step toward commercial availability. The company fabricated a standalone Arbel test chip on TSMC’s 5nm process to assess its performance independently, confirming results already demonstrated within the Maverick-2 deployment. This architecture boasts a 10-wide instruction-issue pipeline and a 480-entry reorder buffer, capable of retiring up to 16 scalar instructions per cycle, alongside four 128-bit vector units for data-parallel workloads. Clock speeds currently reach 2.5 GHz, with plans to achieve 3.4 GHz in the production version utilizing a more advanced process node.

The decision to productize Arbel as a standalone server chip was directly informed by customer feedback. Elad Raz, CEO and co-founder of NextSilicon, said, “The future isn’t just more accelerators – it’s smarter, more powerful CPUs with fewer, stronger cores.” NextSilicon emphasizes that Arbel was designed from the ground up to meet the specific requirements of AI infrastructure, offering a RISC-V alternative that reduces reliance on third-party licensing and roadmaps. Andrea Gallo, CEO of RISC-V International, added, “RISC-V is the most compelling architecture for the future of AI, data center, and HPC workloads.” The Arbel production processor is expected in the first quarter, with NextSilicon actively engaging with potential customers for early access and continued collaboration.

Arbel Architecture: 10-Wide Pipeline and 480-Entry Reorder Buffer

Fabricating the test chip on TSMC’s 5nm process allowed for comprehensive evaluation outside the accelerator context, confirming the core’s capabilities under real-world conditions. This architecture is further enhanced by four 128-bit vector units, designed to accelerate data-parallel workloads crucial for AI inference. While the test chip reached clock speeds of 2.5 GHz, the production processor targets 3.4 GHz, utilizing a more advanced process node to optimize power efficiency and density for demanding data center and HPC environments. The core retains the TAGE branch predictor, engineered to compete with leading x86 and ARM server implementations in prediction accuracy. This design philosophy addresses a growing need for CPUs optimized for agentic AI, where complex workflows demand rapid response times and efficient orchestration.

Extensive silicon evaluations, involving HPC program leads, AI infrastructure architects, and data center operators, have directly informed the architecture of the forthcoming production processor, demonstrating a commitment to co-development with end-users. Clock speeds currently reach 2.5 GHz, with the production version targeting 3.4 GHz and leveraging a more advanced process node for improved power efficiency. Standard coherent CHI interconnect and Linux OS support further enhance its practicality for server and HPC environments.

RISC-V Ecosystem Growth and Data Center Opportunity

The expanding RISC-V ecosystem is maturing beyond academic circles and establishing itself as a viable contender within the enterprise data center, a transition fueled by increasingly standardized software support and a projected compound annual growth rate of 33.1% to over $200 billion. Major Linux distributions, compiler toolchains, and systems software from vendors like Canonical, Red Hat, and NVIDIA now natively support RISC-V, but a performance gap remains at the high end, particularly for emerging workloads demanding a unique balance of parallelism and serial processing.

NextSilicon’s development of the Arbel core directly addresses this need, recognizing that hybrid HPC and AI tasks require both massive compute capacity and efficient serial logic to avoid throughput bottlenecks. This architectural mismatch is particularly acute with agentic AI coding platforms, which, unlike training workloads, rely on autonomous reasoning loops that are fundamentally serial in nature; parsing code, evaluating alternatives, and validating output all demand strong single-thread performance. Elad Raz of NextSilicon deliberately designed Arbel to prioritize single-thread execution speed, acknowledging that existing general-purpose server cores are ill-suited to these emerging demands. NextSilicon’s approach, starting with workload requirements rather than inherited architectural constraints, has resulted in a CPU built for the next generation of AI and HPC systems, leveraging the open ISA of RISC-V to provide customers with greater control.