D-Wave is shifting its focus from simply increasing physical qubit counts to achieving a more practical measure of quantum computing power: 100 logical qubits capable of more than one million error-corrected operations. The company reports this milestone is a key goal in its gate-model roadmap, signaling a maturity in approach and a prioritization of reliable computation over sheer scale. D-Wave intends to reach this benchmark by combining superconducting dual-rail qubits with built-in error detection, on-chip cryogenic control, and a forthcoming error-aware simulator designed to help developers prepare for this new era of quantum computing.
D-Wave’s Dual-Rail Qubits Enable Real-Time Error Detection
D-Wave is targeting a ten-fold improvement in error reduction rates with its novel qubit architecture. This ambition isn’t about brute-force scaling, but about building a system that reliably executes operations, a principle central to D-Wave’s gate-model roadmap. A core component of this strategy is the development of superconducting dual-rail qubits, designed with built-in error detection capabilities. Unlike many current architectures, D-Wave’s approach aims to identify approximately 90% of errors as they occur, significantly reducing the resources needed for quantum error correction. “Error awareness can directly improve the economics, scalability, and practicality of fault-tolerant quantum computing,” explains Trevor Lanting, Chief Development Officer, R&D at D-Wave. This proactive error detection contrasts with systems that attempt to correct errors after they accumulate, potentially requiring exponentially more qubits to achieve reliability.
D-Wave has already demonstrated 99.9% two-qubit fidelities, corresponding to physical error rates of roughly one error per 1,000 operations, a performance level they believe will allow for quantum error-correction cycles running 100 to 1,000 times faster than those found in neutral-atom or trapped-ion systems. The company is targeting a Lambda value of 10, a metric measuring how rapidly errors are reduced with added error-correction capability; this would mean a ten-fold reduction in errors for each increment in error correction, significantly outperforming the industry average of around 2. Lanting asserts that “We believe that Lambda should become a key metric for measuring progress toward fault-tolerant quantum computing because it directly reflects how efficiently a system can turn physical qubits into reliable logical qubits.” Complementing the dual-rail qubits is D-Wave’s on-chip cryogenic control technology, designed to streamline qubit control at scale without sacrificing fidelity, a crucial element for building practical quantum computers.
Superconducting Architecture Achieves Fast Gate Speeds & Scalability
A key innovation lies in D-Wave’s superconducting dual-rail qubits, which incorporate error detection directly into the qubit design. The company has already demonstrated 99.9% two-qubit fidelities. This target significantly surpasses the current industry average of around 2, where each increment of error correction reduces errors by only half. Complementing this hardware approach is proprietary on-chip cryogenic control technology, designed to minimize wiring complexity and maintain qubit fidelity as systems scale, addressing a critical infrastructure challenge for larger quantum computers. The company’s forthcoming gate-model quantum computing simulator, built around this dual-rail architecture, will provide developers with early access to error-aware programming tools and expertise.
Gate-Model Simulator Supports Error-Aware Programming Expertise
Expected to be unique in its design, the simulator is built around the company’s dual-rail architecture and aims to provide developers with early access to error-detection data. This proactive approach allows for application prototyping, the development of error correction techniques, and the cultivation of error-aware programming skills before the full system is realized. Once accessible through D-Wave’s Leap cloud platform, the simulator will support up to 21 qubits, offering both ideal and hardware-emulation modes, alongside Monte Carlo simulations of quantum system dynamics and integration with the D-Wave Ocean SDK. Interested parties can request future access to both the simulator and the complete systems. The development of this simulator reflects a broader industry recognition that qubit quantity alone isn’t the determining factor in achieving commercially viable, fault-tolerant quantum computers; instead, a system’s ability to reliably execute operations at scale is paramount. This built-in awareness dramatically reduces the physical resources needed for quantum error correction, a significant barrier to progress.
Targeting 100 Logical Qubits with One Million Operations
D-Wave is recalibrating the metrics of progress in quantum computing, shifting focus from sheer physical qubit count to the delivery of reliable, error-corrected logical qubits with demonstrable computational capacity. This ambition isn’t simply about scaling up hardware; it’s about engineering a system where computational reliability drives advancement, rather than solely pursuing ever-larger qubit numbers. The company has already demonstrated 99.9% two-qubit fidelities. Beyond error detection, D-Wave is prioritizing the speed at which errors are reduced with increased error-correction capability, measured by a metric called Lambda. The company’s roadmap targets a Lambda of 10, meaning errors should fall by a factor of 10 for each increment in error correction; this contrasts with industry averages around 2, where each increment halves the error rate. Complementing this qubit design is proprietary on-chip cryogenic control technology, reducing the physical infrastructure needed to manage large qubit arrays without sacrificing fidelity.
D-Wave’s roadmap targets a Lambda of 10, which we expect will reduce errors by a factor of 10 for each increment in error correction.
