StealthCores has launched StealthPQ, a post-quantum cryptography IP core designed to fully offload ML-KEM and ML-DSA, the new NIST standards for key establishment and digital signatures. The core incorporates a detailed countermeasure configuration with over 30 specific protections against fault and glitch attacks, including a dual-lockstep controller that erases keys upon fault detection. “The new algorithms solve the quantum problem, but they do not solve the implementation problem,” says StealthCores President Stuart Audley, emphasizing the need for hardware-level security. StealthPQ supports ML-KEM-1024 and ML-DSA-87 parameter sets required for CNSA 2.0 compliance.
StealthPQ Hardware Offload of NIST ML-KEM and ML-DSA
StealthPQ applies cryptographic masking to every secret-dependent operation within the core, a design choice reflecting a comprehensive approach to hardware security. The core’s architecture prioritizes preventing information leakage through power consumption or electromagnetic radiation, bolstering defenses against increasingly sophisticated attacks targeting cryptographic implementations. This masking strategy is central to StealthCores’ approach to security. This is particularly relevant as U.S. national security systems are expected to adopt CNSA 2.0 standards beginning in January 2027, making StealthPQ a timely solution for government and defense applications.
A dual-lockstep controller is a key component of the StealthPQ countermeasure configuration, providing a detailed layer of fault and glitch attack protection. StealthPQ performs each operation in full, from key generation through signing and decapsulation. The host starts an operation through a single AXI4-Lite interface and reads the result when the core signals completion. A detected fault locks the core until all keys are erased.
This proactive approach prevents attackers from exploiting transient errors to extract sensitive information or bypass security mechanisms. The design of StealthPQ focuses on simplifying integration for developers, as Stuart Audley, President of StealthCores, explains, “StealthPQ makes hardware-level cryptography an integration task rather than a complex cryptographic design and verification task.” The core performs all operations, from key generation to signing and decapsulation, through a single AXI4-Lite interface, streamlining the implementation process.
Private keys are generated in secure internal key slots and remain there. Software refers to each key by its slot number, and the shared secret of a key establishment leaves the core on a dedicated output that connects directly to StealthKey or another key store.
Performance benchmarks reveal that the Fast configuration of StealthPQ can complete up to 12,400 ML-KEM-768 encapsulations per second at 200 MHz. At the highest security level, the core achieves up to 9,270 ML-KEM-1024 encapsulations per second, demonstrating its ability to handle demanding cryptographic workloads, StealthCores says. These figures apply to configurations without the countermeasure option, indicating a potential trade-off between performance and security. Customers can also select configurations focusing solely on ML-KEM or ML-DSA, offering flexibility to tailor the core to specific application requirements.
StealthPQ is delivered in both Verilog and VHDL, supporting implementation across a wide range of FPGA families and ASICs. The core joins StealthAES, StealthSHA, and other components to form the complete CNSA 2.0 Security Suite from StealthCores, offering a unified and interoperable security solution, and the company’s suite of cores share common interfaces and a single software library, simplifying development and maintenance.
StealthPQ makes hardware-level post-quantum cryptography an integration task rather than a complex cryptographic design and verification task.
Stuart Audley, President of StealthCores
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