RISC-V Vector Engine Addresses 128 Qubits With One Instruction

Researchers are forecasting significant advances in quantum control for 2026, centered around a new approach leveraging the RISC-V Vector (RVV) engine. The team reports demonstrating the ability to address 128 qubits with a single instruction, a critical step toward scaling quantum systems beyond current limitations. This vectorized quantum control design also incorporates a hardware-based halt-resume protocol capable of restarting pipeline execution in 80 nanoseconds after a mid-circuit measurement, essential for the rapidly developing field of hybrid quantum-classical algorithms. Comprehensive evaluation using RISC-V toolchains and FPGA prototypes showed a 2.52 times speedup in program execution time compared to baseline designs, suggesting a pathway to overcome the classical control bottleneck hindering quantum processor expansion.

Within each circuit family, speedup grows with the number of qubits; for example, performance increased from Bell-4 to Bell-8 by a factor of 52. This progression indicates that larger, more complex quantum algorithms will increasingly benefit from hardware designed to efficiently manage and process a greater number of qubits, moving beyond the limitations of earlier, smaller-scale systems. This capability represents a substantial leap in addressing scalability for quantum systems, moving beyond the sequential control methods that previously limited performance. The ability to operate on a larger qubit space in parallel is critical for realizing the full potential of quantum algorithms, particularly those designed to tackle complex optimization and simulation problems. The hardware-based halt-resume protocol, achieving a restart time of 80 nanoseconds after a mid-circuit measurement, is crucial for enabling rapid iteration in hybrid quantum-classical programs.

This speed is essential for minimizing latency and maximizing the efficiency of algorithms that require frequent communication between the quantum processor and classical control systems. Looking ahead, the implications of these findings extend beyond mere speed improvements; the demonstrated scalability suggests a pathway towards building quantum computers capable of tackling problems currently intractable for even the most powerful supercomputers. The team’s work highlights the importance of instruction set architecture (ISA) design in unlocking the potential of quantum hardware. The researchers state, “This demonstrates that larger quantum circuits, in terms of qubit count, can extract greater performance benefits from our vectoring ISA,” emphasizing the role of software optimization in maximizing hardware capabilities. The observed gains are not simply a matter of adding more qubits, but rather of designing a control system that can effectively harness their collective power.

The fact that different circuit families exhibit varying degrees of speedup underscores the need for adaptable control architectures capable of optimizing performance across a diverse range of quantum algorithms. The interplay between qubit count, ISA design, and efficient control protocols will be a defining characteristic of quantum computing development in the coming years, and will determine the feasibility of solving increasingly complex problems.

Advantage in parallel operations: HiSEP-Q 2

The HiSEP-Q 2 system demonstrates a departure from traditional instruction set architectures, leveraging RISC-V vector extensions to address a critical bottleneck in scaling quantum algorithms. Current quantum control systems often struggle to efficiently manage the simultaneous execution of operations across multiple qubits, limiting the speed and complexity of achievable computations; however, this new approach promises to unlock substantial performance gains by streamlining the delivery of instructions to an array of qubits. Specifically, the system is designed to handle layers of two-qubit gate operations with increased efficiency, a capability that will become increasingly important as qubit counts continue to rise in advanced quantum processors. This contrasts sharply with baseline instruction set architectures, which require multiple instructions to perform the same operation across a comparable number of qubits.

The team reports demonstrating that algorithms with high parallelism in two-qubit gate operations benefit most from this architecture, achieving a 52 times speedup in program execution time for the Bell-8 algorithm, both of which rely heavily on independent, parallel CX gate pairs. The researchers explain that the system packs an entire layer of these operations into a single vector instruction. This year will also see increased focus on optimizing the interaction between quantum and classical processing units, and the HiSEP-Q 2 system’s architecture is designed to facilitate this integration. The RISC-V foundation provides a standardized platform for developing and deploying custom instructions, allowing for seamless communication between the quantum control hardware and classical processors. This interoperability is critical for building practical quantum computers that can solve real-world problems, as it enables efficient data transfer and control signaling between the two domains. The implications of this technology extend beyond simply accelerating existing algorithms.

By reducing the overhead associated with instruction delivery, the HiSEP-Q 2 system effectively increases the available computational resources for solving complex problems. This could pave the way for the development of new quantum algorithms that were previously impractical due to their computational demands. The development of HiSEP-Q 2 highlights a growing trend in quantum computing: the convergence of hardware and software optimization. By designing a custom instruction set architecture tailored to the specific needs of quantum algorithms, the researchers have demonstrated the power of co-design in achieving significant performance gains. As quantum processors continue to scale in size and complexity, this approach will become increasingly important for overcoming the challenges of control and communication. The system’s architecture, with its emphasis on parallel operations and efficient instruction delivery, positions it as a promising platform for future quantum computing research and development.

Limitations with sequential dependencies: Circuits with deep sequential dependencies, such as QAOA-8/16 and QFT-8, contain long chains of dependent CX gates that must be executed sequentially

Industry leaders predict that even with the accelerating advancements in quantum control systems, certain architectural limitations will continue to pose challenges for executing complex quantum algorithms in 2026. These circuits are characterized by extended chains of CX (controlled-NOT) gates that, by their very design, must be executed in a strict, sequential order, hindering the potential for parallelization offered by emerging quantum hardware. This inherent sequentiality prevents the full exploitation of a new RISC-V Vector-based quantum control approach, which is designed to pack instructions for multiple qubits into single vector instructions. The inability to vectorize these dependent operations limits the performance gains achievable with HiSEP-Q 2.0, a system designed to address scalability in quantum systems.

As the researchers explain, “Circuits with deep sequential dependencies, such as QAOA-8/16 and QFT-8, contain long chains of dependent CX gates that must be executed sequentially.” This constraint means that while the hardware is capable of addressing 128 qubits in a single instruction, the structure of these specific algorithms prevents it from fully leveraging that capability. The system yields marginal to no performance advantage for these specific workloads, demonstrating that architectural improvements alone are insufficient to overcome algorithmic limitations. The performance characteristics of the new quantum instructions are being meticulously analyzed to understand these bottlenecks. Measurements of latency and throughput reveal that the speed of operations like QV. SINGLE, QV. ROT. G, and QV. ROT. V closely mirrors the number of useful events occurring, indicating near one-to-one event emission per cycle in a stable state. However, instructions like QV. PAIR and QV. ROT. G incur a slight latency increase with larger qubit counts due to fixed stream-framing and pipeline-alignment overheads.

The system’s ability to group factors of m4 and m8 is restricted for QV. ROT. V, further limiting optimization possibilities. While the observed latency generally scales linearly with the number of encoded qubits, the initial configuration instructions introduce a delay before the quantum event stream begins. Experts anticipate that the precise timing of these operations will be critical for hybrid quantum-classical programs. The hardware-based halt-resume protocol, a key feature of the system, is designed to minimize disruption during mid-circuit measurements. However, this speed is only fully realized when the underlying quantum circuit does not contain long sequential dependencies. The researchers note that after measure_done is observed, this delay, while minimal, accumulates with each sequential gate, impacting the overall execution time of complex algorithms.

To accurately assess throughput, the team has adopted a nuanced approach, separating exported data into dynamic payload, bits that change with each quantum event, and semantic metadata, bits that remain constant. This calibration method avoids overstating throughput by repeatedly counting static metadata while preserving the essential information needed to interpret the quantum event stream. Analysis reveals that QV. SINGLE maintains high throughput due to its simple structure, while QV. ROT. V exhibits similar levels for legal configurations. Conversely, QV. PAIR and QV. ROT. G show lower throughput due to smaller per-event payloads and fixed framing overheads. As qubit counts increase, these overhead cycles are partially amortized, but still contribute to a slight reduction in average throughput. Resource utilization studies on the ZCU216 FPGA demonstrate that the HiSEP-Q 2.0 design scales favorably with qubit count.

The entire 32-qubit configuration consumes 14,888 LUTs, 15,492 FFs, and 10 DSP blocks, occupying less than 4% of the available resources. The Vector Engine dominates LUT usage, while the Quantum Dispatcher dominates FF usage. Importantly, the scalar/vector front-end remains constant regardless of qubit count, and the Quantum Dispatcher scales linearly with the number of qubits, adding approximately 90 LUTs and 263 flip-flops per qubit. This linear scaling, coupled with the ability to reconfigure the SEW field at runtime, suggests that the architecture is well-positioned to handle future Fault-Tolerant Quantum Computing workloads. The researchers state that HiSEP-Q 2.0 is “ready for FTQC-scale qubit counts without architectural redesign.” However, the limitations imposed by sequential dependencies in certain algorithms will remain a key area of focus for optimization in the coming years, requiring a combined approach of algorithmic innovation and hardware refinement to unlock the full potential of quantum computation.