The critical measure of performance for neutral-atom quantum processors is not the total number of gates, but the number of sequential laser operations, known as CZ-depth, required to execute a circuit. Working with QuEra, Classiq has developed a hardware-aware scheduling capability that reorders circuits to minimize these layers, directly impacting accumulated error, a key challenge in these platforms where “dominant two-qubit errors scale primarily with the number of entangling layers rather than the number of gates within a layer.” Physical qubits in this system are encoded in hyperfine ground states of 87Rb atoms trapped in optical tweezers, with two-qubit gates realized by a single global entangling pulse exciting atoms to Rydberg states.
Randomly select a swappable pair of adjacent CZ gates
Reducing the sequential application of CZ gates, referred to as CZ-depth, directly impacts performance on neutral-atom quantum processors more than simply minimizing the total gate count. The approach involves identifying and swapping adjacent CZ gates within a quantum circuit, a process that can significantly alter the overall execution time and fidelity. This optimization isn’t about eliminating gates, but about strategically rearranging them to minimize the accumulation of errors during computation.
This unique implementation means that each entangling operation requires precise laser control and timing, making the number of sequential laser operations, the CZ-depth, a critical metric. The team’s scheduling capability analyzes the circuit and identifies pairs of adjacent CZ gates that can be swapped without altering the final result, effectively flattening the entangling layers. The impact of this optimization extends beyond theoretical improvements. It directly addresses the challenges of maintaining qubit coherence.
By minimizing the CZ-depth, the system reduces the time qubits spend in excited Rydberg states, decreasing the probability of decoherence and improving the overall fidelity of the computation, QuEra says. This approach represents a shift in quantum compilation strategies, prioritizing the structure of the circuit over sheer gate minimization, and offers a pathway to more robust and scalable neutral-atom quantum processing. The ability to randomly select and swap adjacent CZ gates is a key component of this strategy, allowing for a more flexible and efficient use of hardware resources.
Swap the order of the selected gates
Minimizing the sequential application of controlled-Z (CZ) gates directly impacts the performance of neutral-atom quantum processors, as the number of these layers, known as CZ-depth, is a more critical metric than total gate count. The team’s approach focuses on identifying swappable pairs of adjacent CZ gates, a technique that allows for a more efficient use of the hardware’s capabilities, according to QuEra.
This is particularly relevant because the researchers report that this reordering can significantly decrease the overall error rate. This hardware-aware scheduling capability is designed to work in tandem with the unique characteristics of neutral-atom platforms, where precise laser control and timing are essential for qubit manipulation.
Recompute the CZ-depth
A probabilistic acceptance rule governs the reordering of controlled-Z (CZ) gates, allowing for increases in circuit depth in exchange for potential overall optimization. Classiq developed a hardware-aware CZ scheduling capability that reorders circuits to match how neutral-atom hardware actually executes, cutting the laser pulses required to run the same algorithm. The team uses a rapid layering technique, a form of topological sorting, to assess the resulting CZ layers after gate reordering.
The acceptance of a swapped gate pair hinges on whether the reordering reduces the overall depth; if it does, the swap is automatically accepted. However, if a swap increases depth by an amount denoted as Δ, the swap is accepted with a probability determined by the temperature parameter, T. This introduces an element of exploration, allowing the algorithm to escape local minima in the search for an optimized circuit structure.
The algorithm does not guarantee a reduction in CZ-depth with every swap, but aims to find a configuration that minimizes it over many iterations. This method differs from traditional quantum compilation strategies that prioritize gate minimization, instead focusing on the structure of the circuit and its impact on error accumulation.
Gilad Kishony and Avi Elazari, the authors of the study, explain that the core principle of the optimization process is “If the new depth is smaller → accept the swap.” By strategically accepting swaps that may temporarily increase depth, the system can potentially achieve a lower overall CZ-depth and, consequently, reduce the accumulation of errors during computation.
Lower the temperature T gradually (cooling schedule) to refine the solution over time
A gradual reduction in a parameter known as ‘temperature’ refines the circuit optimization process, allowing the system to escape configurations that appear optimal but are, in fact, local minima. The approach builds upon formal commutation analysis, dependency-graph refinement and simulated annealing to consistently reduce the number of laser pulses required for circuit execution. Evaluation of 316 circuits revealed an average CZ-depth improvement of approximately 11.0 percent through this hardware-aware reordering.
Analysis of application-specific circuit families showed savings ranging from 10 to 40 percent across several categories, with some structured workloads exceeding 40 percent reduction. These results demonstrate the optimization’s broad applicability, extending from chemistry simulations to quantum approximate optimization algorithms and even error-correcting code subroutines. The team integrated constraints specific to QuEra’s parallel CZ architectures and laser-pulse scheduling, ensuring compatibility with the hardware’s error models.
This optimization was designed to emit Quantum Assembly Language (QASM) with reordered controlled-Z gates while maintaining deterministic compilation and preserving algorithmic semantics, the firm reports. Classiq’s work complements existing parallelization tools by embedding device-specific scheduling considerations directly into the circuit generation and compilation flow, ultimately delivering higher fidelity, shorter runtimes and improved scalability on quantum systems.
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