ParityQC’s new optimizer cuts gate count for quantum problems

IBM Quantum Network members can now test a new optimization tool with a 30-day free trial. ParityQC has launched the Parity Twine Optimizer within the IBM Qiskit Functions Catalog, bringing its record-setting compiler technology, originally demonstrated with the Quantum Fourier Transform, to a wider audience, the company says.

The optimizer reduces two-qubit gate overhead, enabling the execution of larger, denser optimization problems on current quantum hardware. “By offering the Parity Twine Optimizer as an IBM Qiskit Function, we are providing the quantum community with access to a tool with what we currently show to be the most efficient quantum compiler available for larger and more connected problems to run on real hardware,” say ParityQC co-CEOs Magdalena Hauser and Wolfgang Lechner.

Parity Twine Optimizer Reduces Gate Count for Quantum Optimization

The Parity Twine Optimizer delivers a significant reduction in gate count and depth for quantum optimization, enabling the execution of denser problems on current hardware. Initial results demonstrate the technology minimizes two-qubit gate overhead when compiling industry-relevant optimization challenges, a benefit stemming from the structure of Parity encoding itself and maintaining consistency as problems scale. This hardware-independent compiler, also available through ParityQC’s ParityOS software, expands access beyond IBM’s platform with future integrations planned.

The technology eliminates the need for costly SWAP operations, allowing full use of existing quantum processors by minimizing circuit depth and two-qubit gate overhead. ParityQC, founded in 2020 and headquartered in Innsbruck, Austria, designs hardware-efficient quantum optimization algorithms using parity-encoded quantum circuits. Partnerships with companies like Classiq and NEC demonstrate a commitment to broader integration; Classiq is combining efforts to reduce quantum circuit complexity, while NEC implemented ParityQC’s architecture in its quantum processor with commercial deployment of ParityOS, according to IBM.

“Compile your circuits with maximum efficiency and minimal overhead in two-qubit gates,” states promotional material accompanying the launch, highlighting the technology’s potential to run larger problems on real hardware and preserve algorithm quality for faster execution. In May 2026, ParityQC and IBM executed a 52-qubit quantum Fourier transform on an IBM Heron processor with reduced error rates, nearly doubling the prior benchmark of 28 qubits.

QFT-Record Compilation Powers ParityQCArchitecture’s Efficiency

The Parity Twine Optimizer builds on a compilation technique initially proven through a record-setting 52-qubit Quantum Fourier Transform executed on IBM’s Heron processor in May, now extended to broader quantum optimization challenges. This expansion demonstrates the versatility of ParityQC’s architecture, moving beyond a single algorithm to address a wider range of computational problems. The optimizer’s core strength lies in minimizing two-qubit gate overhead, a critical factor limiting the scale of problems solvable on near-term quantum hardware.

By reducing this overhead, ParityQC enables the execution of larger and denser optimization instances than previously possible. QUDORA and Alpine Quantum Technologies are also partners, enhancing algorithm efficiency on trapped-ion hardware and implementing the ParityQC architecture on their respective processors.

The impact of the Parity Twine Optimizer extends to practical application, eliminating the need for costly SWAP operations that traditionally hinder quantum circuit performance, the company says. This reduction in circuit depth and gate count not only accelerates execution but also minimizes error accumulation, a persistent challenge in quantum computing. Founded in 2020 and currently employing approximately 49 people, ParityQC continues to refine its architecture, with ongoing collaborations including a partnership with DLR and IQM Quantum Computers to further expand its reach and capabilities.

IBM Qiskit Integration Enables Access to Parity Twine Compilation

ParityQC reports the technology, initially validated through its QFT results, now applies its hardware-efficient compilation to industry-relevant problems, offering a new avenue for scaling quantum solutions. This expansion uses the company’s ParityQC Architecture, extending its impact beyond a single algorithm and providing a versatile tool for developers. Scott Crowder, Vice President of IBM Quantum Adoption and Business Development, emphasized the benefit for IBM Quantum Network members, stating, The optimizer’s design prioritizes efficiency on current hardware, a critical factor given the limitations of qubit counts and coherence times, the company states.

Access is facilitated through a 30-day free trial, allowing immediate testing without requiring changes to existing workflows or upfront commitments. Beyond Qiskit integration, the underlying compiler is accessible through ParityOS, suggesting future expansion to other quantum computing platforms and access routes. The company’s Austrian headquarters in Innsbruck continues to refine this architecture, supported by partnerships with QUDORA, NEC, and Classiq, among others, to enhance algorithm performance across diverse hardware types.

More like this

Quantum AlgorithmsOQC and Trust Base test quantum methods for financial risk

Quantum Research NewsNTU-IBM Quantum Hub shows shallow circuits beat language models on key tasks

Quantum Computing NewsPsiQuantum team shares R&D at IEEE Quantum Week in Toronto

Quantum AlgorithmsResearchers Bound Error Weight Controlling Quantum Memory Failures