IBM is building IBM Quantum Starling, a fault-tolerant quantum computer slated to launch in 2029 and capable of running circuits with 100 million quantum operations on 200 qubits. A modular architecture, detailed in a 2025 paper, underpins Starling’s design and enables a significant reduction in the resources needed for error correction; for the same logical error rate, the system requires roughly 10 times fewer physical qubits than prior approaches. This scalability stems from the implementation of bivariate bicycle quantum low-density parity check (qLDPC) error correction codes, first introduced in a 2024 Nature publication.
qLDPC Architecture Reduces Qubit Needs for Starling
The modular architecture underpinning IBM Quantum Starling achieves a ten-fold reduction in physical qubit requirements for a given logical error rate compared to previous quantum error correction approaches. Assembling modules, each containing quantum memory and a logical processing unit, allows for scalable logic operations and interconnectivity via l-couplers. This modularity is not merely a structural choice. It directly addresses the escalating resource demands of fault-tolerant quantum computing.
These modules are further integrated with sophisticated cryogenic and control systems, maintaining ultra-cold operating temperatures essential for qubit coherence. IBM Quantum Network has validated the performance of these components, demonstrating progress across multiple fronts. A year ago, the team announced IBM Quantum Loon, a system designed to demonstrate key elements of the qLDPC codes, including qubit reset circuits and c-couplers for linking qubits within a chip, a prerequisite for the six-way qubit connectivity needed to implement the qLDPC code.
Since then, Loon achieved qubit relaxation times (T1) of approximately 200us with reset time constants ranging from 20 to 40 nanoseconds, and its gates exhibited median error rates near 0.3%. The ultimate goal for Starling, however, is to reach T1 in the millisecond range and gate errors below 0.01%, a target informed by recent performance on IBM Quantum’s Heron and Nighthawk processors. “We routinely measure gate errors in the high 0.01% range on Heron and Nighthawk—going as low as 0.04%,” the team reports, indicating the feasibility of achieving these ambitious specifications.
New designs focused on lowering risk and increasing yield for the modular qLDPC code processors directly benefit Starling’s development. The validation of the c-coupler approach and the reduction in required Josephson junctions represent significant steps toward optimizing future quantum processor designs. Decoders, classical algorithms vital for identifying and correcting errors in quantum circuits, are also undergoing refinement.
The latest version of IBM’s application-specific integrated circuit (ASIC) has demonstrated noise characteristics that match and even exceed the gate performance of room-temperature control systems. Starling will ultimately rely on a modular, real-time control system built on diverse classical information flows, extending the modular design philosophy into the control layer with CPUs, field-programmable gate arrays (FPGAs) and ASICs. Interconnect technologies capable of scaling to large systems without compromising latency are critical to this control system.
This year, IBM Quantum Network validated several standards-based interconnect technologies through small-scale prototypes, confirming their suitability for Starling’s requirements. The team continues to refine logical processing units (LPUs) and reduce the overhead associated with magic state injection, further optimizing the architecture.
While the main architecture for Starling remains consistent, the pathway chosen has been validated, and clear next steps for continued progress have been identified. The advances discussed above, including the validated c-coupler approach, reduced qubit connection requirements, and improved decoder algorithm performance, represent substantial progress toward realizing the promise of fault-tolerant quantum computing with IBM Quantum Starling.
Loon Demonstrates Key Components for Error Correction
These measurements, taken since Loon’s initial announcement a year ago, validate key aspects of the qLDPC error correction codes central to Starling’s design and represent progress toward the system’s ultimate goal of millisecond-range T1 times and gate errors below 0.01 percent. The team’s work on these l-couplers is particularly important, as Starling will ultimately require over 100 per module, each operating with error rates below 0.1 percent to maintain performance.
Progress in improving the reliability and repeatability of these couplers is therefore a key focus. Beyond the physical qubits themselves, the development of sophisticated cryogenic and control systems is equally vital. IBM has introduced a modular cryogenics design intended to smoothly link processing modules together, forming the backbone of future quantum systems at the scale required for Starling.
C-Coupler Advances Enable Dense Chip Connections
Increasing the density of connections between qubits without sacrificing performance is a central challenge in scaling quantum processors, and recent work demonstrates a viable path forward through advances in c-coupler technology. IBM Quantum Network has successfully increased the number of c-coupler layers used in their chips from two to three, with plans to reach four or more, enabling more complex routing and shortening the longest connections these couplers must make.
The validation of c-couplers as a means of establishing these connections is bolstered by findings that increasing the number of layers introduces only a minimal reduction in quality factor. This allows for greater flexibility in chip design and the potential to circumvent limitations imposed by physical constraints. Innovations in the qLDPC code itself have reduced the required connections between qubits from six to five, simultaneously delivering a reduction of 20 to 100 times in logical errors.
These combined improvements represent a step toward building a scalable, fault-tolerant quantum computer. Beyond the qLDPC code, IBM Quantum Network has also focused on reducing the overall complexity of the quantum processing unit (QPU) by minimizing the number of Josephson junctions required.
The team has more than halved the number of these critical components, decreasing the count from approximately 5,000 to 2,000. This reduction is projected to substantially improve device yield; with a target junction yield of 99.95%, the team estimates that one out of three processors will be fully functional with 2,000 junctions, compared to only one out of twelve with 5,000 junctions.
The ability to link multiple quantum processors together is also important for scaling to larger systems. Recent experiments have demonstrated successful connections between two Nighthawk processors using four l-couplers. These connections achieved an average error rate of 1%, with the best result registering at 0.7%. This achievement validates the potential of l-couplers to establish long-range connections between processing modules, a key requirement for the modular architecture of IBM Quantum Starling.
The company’s goal is to construct a fully real-time control system based on diverse classical information flows, ensuring smooth communication and coordination between the processing modules. The convergence of these developments suggests a clear path toward realizing a fault-tolerant quantum computer with significantly reduced resource requirements.
Relay-BP Decoder Meets Starling’s Error Rate Goals
The decoder’s performance, detailed in recent work, demonstrates improved logical error rates while simultaneously reducing the computational demands of the decoding process itself. Previously, achieving acceptable error rates necessitated substantial computational resources for decoding, a bottleneck for scaling quantum systems. The team’s work shows that the framework is capable of delivering the necessary performance for Starling’s modular approach to scalability. This chip is intended to improve logical error rates and boost the overall performance of the Starling system.
The need for robust inter-module connectivity is also being addressed through the development of l-couplers, which link processing modules together. Scaling to the number of l-couplers needed for Starling, over 100 per module, requires maintaining low error rates, and the team is focused on improving both reliability and repeatability. The modular design extends to the cryogenic systems used to house the quantum processors.
“Transferring coherence times from our test devices, which are currently in the single digit millisecond range, will also help facilitate lower error rates,” the team reports. The team’s focus on modularity and resource reduction is important for overcoming the challenges of building and operating large-scale quantum systems. The custom decoder ASIC, with its advanced 2nm technology, is expected to deliver further improvements in performance and efficiency.
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