STMicroelectronics is launching the STM32G5 microcontroller on November 3, 2026, to proactively address emerging regulations requiring quantum-resistant algorithms. The new device consistently targets SESIP Level 3 and PSA Level 3 certifications, allowing engineers to meet current and upcoming requirements without sacrificing performance or adding components. The company states that the STM32G5 offers robust, built-in security that supports current and upcoming compliance efforts, and its Cortex-M33 core combines established TrustZone features with dedicated support for post-quantum cryptography.
STM32G5 Hardware Accelerates NIST-Approved Post-Quantum Cryptography
The STM32G5 microcontroller incorporates a hardware crypto core designed to accelerate all algorithms approved by the National Institute of Standards and Technology for post-quantum cryptography. This inclusion addresses emerging regulations from bodies like the European Commission and NIST itself, which are mandating support for quantum-resistant algorithms in computer systems. The device will initially support LMS, ML-KEM, ML-DSA and SLH-DSA, stateful and stateless hash-based algorithms intended to withstand attacks from future quantum computers.
Preparing infrastructure now is critical, as the industry anticipates the eventual ability of quantum computers to break existing asymmetric cryptography. Secure key storage is achieved through a hardware key wrapping mechanism and Secure Crypto Engines, isolating keys during use to prevent disclosure and maintain system integrity.
These keys are essential for device authentication, software measurements, secure communication, secure boot, and firmware updates, requiring careful management throughout the product’s lifecycle. The STM32G5’s approach aims to mitigate catastrophic damage from compromised keys during both manufacturing and field operation.
The company emphasizes that the ability of quantum computers to compromise classic asymmetric cryptography is not a question of if, but when. This hardware acceleration is intended to provide a solution for developers facing these new regulatory requirements and potential vulnerabilities, representing a step toward future-proofing designs against quantum computing threats and ensuring continued data security.
STM32G5 TrustZone Isolates Secure Boot and Key Management
The STM32G5 microcontroller employs TrustZone technology to create a distinct boundary between secure and non-secure processing domains, a critical feature for protecting sensitive operations. This isolation prevents a compromised application running in the non-secure area from accessing or disrupting the secure boot process and key management functions residing within the trusted domain. Consequently, the attack surface available to malicious actors is significantly reduced, simplifying system recovery should a breach occur as only the non-secure domain requires resetting.
The architecture is particularly relevant as evolving standards like the Security Protocols and Data Models (SPDM) increase scrutiny on authentication, attestation and key exchanges. Meeting requirements for modular common redundant power supplies (M-CRPS), as defined by the Open Compute Project (OCP), also demands secure boot and firmware update capabilities.
STM32G5 Meets Evolving Regulatory Requirements for Secure Firmware
This capability allows teams to meet current and upcoming regulatory requirements, offering greater control over the device lifecycle and increased design flexibility. Secure key management is paramount, as compromised keys could have catastrophic consequences during manufacturing and field deployment. The STM32G5’s hardware-based approach ensures these keys remain protected, eliminating the need for a separate secure element in the bill of materials. This architecture is particularly relevant as new regulations demand unique IDs and certifiable keys to meet the latest attestation requirements for secure firmware installations, over-the-air updates and root secure services.
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