SpinHex Architecture Predicts 0.18% Entangling Gate Error

Rubén M. Otxoa of Hitachi Cambridge Laboratory and colleagues propose a new spin-qubit architecture, SpinHex, using spinless multi-electron quantum dots as low-crosstalk couplers arranged in a hexagonal lattice. The design predicts a 0.18% error rate threshold for entangling gates, potentially easing the path toward practical quantum error correction. Researchers detail that implementing the rotated XZZX surface code with this architecture would require 4480 physical qubits per logical qubit, ultimately needing a 2.6cm² chip to host 10,000 logical qubits.

SpinHex Architecture: Multi-Electron Couplers for Spin Qubits

SpinHex architecture uses spinless multi-electron quantum dots as couplers between qubits, a departure from traditional coupling methods intended to minimize crosstalk. These unique couplers, occupied by multiple electrons or holes, create a substantial separation between the connecting quantum dot arrays, reducing capacitive crosstalk that poses a challenge to two-dimensional integration for surface code implementation. Rubén M. The SpinHex design arranges spin qubits in a hexagonal lattice, connecting one-dimensional arrays of quantum dots via three-way junctions.

This configuration differs from typical T-junctions by employing these spinless multi-electron couplers to link the terminal ports of three one-dimensional quantum dot arrays in a two-dimensional plane. The core innovation lies in the ability of these multi-electron couplers to mediate voltage-controlled Heisenberg exchange between spin qubits, enabling coherent multi-qubit operations with reduced interference. The team focused on depletion gates in their design, acknowledging that adaptations would be necessary for implementation in SiMOS or Si/SiGe platforms.

Such platforms would require the addition of micromagnets or microwave antennas for effective spin control. “SpinHex provides a 2D arrangement of spin qubits in a hexagonal lattice,” the authors summarize, emphasizing the architecture’s potential for scalable quantum computing. The use of spinless quantum dots as couplers represents a novel approach to mitigating interference and maintaining qubit coherence, essential for reliable quantum computation. The design’s emphasis on compatibility with existing semiconductor fabrication technology suggests a pathway towards practical scalability, a key hurdle in the development of quantum computers.

Hexagonal Lattice Design Minimizes Capacitive Crosstalk

These couplers, controlled by voltage signals, mediate fast Heisenberg exchange, enabling coherent multi-qubit operations essential for complex quantum computations. The architecture’s design specifically addresses the challenges posed by crosstalk in densely packed qubit arrays, a significant hurdle in scaling up quantum processors. Numerical studies of this implementation, conducted with a circuit-level noise model, predict a threshold of 0.18% for the error rate of entangling gates.

The team focused on double quantum dots connected via these multi-electron couplers, anticipating low capacitive crosstalk and simplified device tuning. Unlike previous approaches relying on T-junctions, SpinHex employs these spinless multi-electron couplers to create larger separation between coupled spin qubits. This increased separation directly reduces capacitive crosstalk, a major source of error in quantum systems. However, the design prioritizes compatibility with existing semiconductor fabrication technology, suggesting a potential pathway toward scalable production.

The SpinHex architecture’s core unit, the spinless quantum dot, mediates voltage-controlled Heisenberg exchange between up to three spin qubits in two dimensions. This configuration is expected to simplify device tuning and facilitate low-crosstalk operation, allowing for the maintenance of qubit coherence. The work introduces a semi-realistic device design for operating surface codes, offering a potential solution to the challenges of two-dimensional integration and capacitive interference.

Rotated XZZX Surface Code Implementation in SpinHex

The SpinHex architecture predicts a 0. This performance benchmark stems from a detailed numerical study of the rotated XZZX surface code implemented within the SpinHex framework, evaluating its resilience to device-specific circuit-level noise. The implementation of stabilizer circuits, essential for the XZZX code, was modeled for a (N_x,N_y) = (2,3) unit cell, demonstrating how the architecture can host a rotated surface code of a given distance, ‘d’, within a (d+1)x(d+1) square lattice.

“A SpinHex device consisting of a (d + 1)×(d + 1) square lattice of unit cells can always host a rotated surface code of distance d,” the authors state, highlighting the inherent scalability of the design. The work details how two-qubit stabilizer operations, such as CZ and CX gates, are implemented through SWAP operations across the multi-electron couplers, further illustrating the architecture’s operational mechanics.

Entangling Gate Error Threshold of 0.18% in SpinHex

Simulations of the SpinHex architecture predict an entangling gate error rate threshold of 0.18%, a figure suggesting a substantial reduction in the resources needed for practical quantum error correction. Evaluating the architecture’s potential, researchers predict that achieving a logical qubit requires 4480 physical qubits, operating with an overall error rate of 10^-12 and maintaining entangling gate fidelities of 99.99%. The simulations employed the pymatching implementation of the minimum-weight perfect matching decoder to assess performance, modeling errors using Pauli channels dependent on the operation performed.

The logical error rate was then plotted as a function of code distance, revealing the threshold for reliable operation. The study further explored the relationship between code distance and gate error rate, extrapolating performance to the TeraQuop regime, a measure of quantum computational power.

The device-specific noise model considered errors introduced by swapping spin qubits across multi-electron couplers, a key component of the SpinHex design. “We predict a threshold of 0.18% for the error rate of the entangling gates,” the authors state, highlighting the potential for significant improvements in quantum error correction.

Scalability: Physical to Logical Qubit Ratio

Achieving the TeraQuop regime demands careful consideration of physical to logical qubit ratios, and simulations suggest a path forward with the SpinHex architecture. Extrapolating from a minimal (2,3) SpinHex device, researchers assessed the number of physical qubits needed to achieve various error correction levels. The projected scalability is further supported by estimates of chip area requirements. Assuming an error rate of 0.0001 and a (2,3) SpinHex device, the simulations indicate a footprint of approximately 2.6cm² is sufficient to host 10,000 logical qubits.

Chip Size Estimate for 10,000 Logical Qubits

Simulations indicate a remarkably compact footprint for a large-scale quantum computer built on the SpinHex architecture; a chip measuring approximately 2.6 square centimeters is sufficient to accommodate 10,000 logical qubits operating in the teraquop regime. This estimate, detailed in recent work, suggests a pathway toward physically realizable quantum processors capable of sustaining trillion-operation computations. 0001. This threshold, determined through extensive numerical simulations of device-specific circuit-level noise, suggests a potentially significant leap toward practical quantum error correction.

Realizations of 1D Quantum Dot Arrays within SpinHex

These multi-electron couplers (MECs) offer increased separation between quantum dots, a design intended to minimize capacitive crosstalk, a common issue in two-dimensional surface code implementations. The design incorporates three potential realizations of the 1D quantum dot arrays, each differing in the placement of occupied quantum dots and the method of information swapping. These variations aim to optimize information transfer and minimize errors during quantum operations. The team anticipates challenges with two-dimensional integration, particularly managing crosstalk in the couplers that connect the 1D arrays.

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