SEEQC reports achieving approximately 50% improvement in key decoding performance metrics by integrating its chip-based pre-decoder with NVIDIA Ising, a combined advancement in latency and logical error rate. The company’s Digital Link and NVIDIA NVQLink established an industry first digital interface optimized decoder architecture, enabling low-latency communication between quantum and classical computing environments, SEEQC says.
“We believe the future of quantum computing will be enabled by the tightest possible integration of quantum processors with advanced high-performance computing infrastructure,” said John Levy, Chief Executive Officer of SEEQC, as the results incorporate realistic decoder latency for future scalability.
Digital Link and NVQLink Enable 50% Decoding Performance Gains
This combined improvement, realized within a simulated quantum processor, incorporated realistic latency expectations for scaling quantum systems, moving beyond purely theoretical gains. The performance gains stem from a specialized processing approach where SEEQC’s chip-based pre-decoder operates closer to the qubits, reducing the data transferred to classical computing systems and accelerating decoding functions.
This architecture addresses critical bottlenecks in scaling fault-tolerant quantum systems, where the overheads associated with error correction can increase exponentially. “Quantum error correction is fundamentally a systems challenge, where latency, data movement and logical error performance all become increasingly critical as quantum processors scale,” explained Matt Hutchings, Chief Product Officer of SEEQC. Reducing these overheads and performance demands on the quantum processor itself is therefore paramount to achieving practical scalability.
SEEQC’s Digital Link and NVIDIA NVQLink played a central role in enabling this performance boost, providing the framework for efficient communication, according to the company. The integration of these technologies facilitated a tightly coupled, multi-stage decoding process, a design the company believes is essential for future quantum computers. “By combining SEEQC’s digital pre-decoder architecture and Digital Link with NVQLink and the NVIDIA Ising pre-decoder, we demonstrated how a tightly integrated, multi-stage decoding architecture can materially improve key performance metrics,” Hutchings added.
SEEQC’s digital quantum control technology, previously published in Nature Electronics, has already demonstrated high gate fidelities exceeding 99.9% at nanowatt-scale power consumption, showing the potential for energy-efficient quantum computing, the firm reports. The current work builds upon this foundation, aiming to evaluate further opportunities to enhance both the performance and scalability of quantum error correction and other hybrid quantum-classical workloads.
The implications of this work extend to the broader quantum computing ecosystem, as open models like NVIDIA Ising and open interfaces like NVQLink empower quantum builders to accelerate their hardware advancements. “These results demonstrate the role SEEQC’s digital chip technology can play at that critical interface.
Bringing specialized processing closer to the qubits while connecting efficiently to GPU-accelerated computing provides a pathway toward quantum systems that can operate at significantly greater scale.” The next phase of development will focus on integrating these system-level components to achieve chip-to-chip integration of a quantum processor within an advanced HPC infrastructure.
Quantum error correction is fundamentally a systems challenge, where latency, data movement and logical error performance all become increasingly critical as quantum processors scale.
Matt Hutchings, Chief Product Officer of SEEQC
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