Researchers Redesign Neural Decoders and Evaluate Accuracy for 161-Qubit Codes

Ge Yan of Nanyang Technological University, and colleagues, are challenging conventional thinking regarding neural decoders used in quantum error correction. Optimising decoding algorithms is key to practical, scalable quantum computation, a step currently limited by a trade-off between speed and accuracy, often measured in microseconds. Their work, focusing on surface-code decoding with up to 161 physical qubits (code distance d=9), systematically evaluates five neural decoder architectures and introduces a compression pipeline for implementation on FPGA hardware. The findings highlight that the scale of training data, rather than architectural complexity, is the primary driver of near-term performance, and that INT4 quantization is essential for meeting real-time latency goals, offering vital guidance for developing viable neural quantum error correction systems.

INT4 quantization and dataset scaling enable sub-microsecond surface code decoding on FPGAs

Decoding latency for surface-code quantum error correction dropped to below 1 microsecond, a reduction previously impossible with existing neural network architectures. Real-time error correction on field-programmable gate arrays, or FPGAs, is now unlocked, which is key for stabilising quantum computations. A larger training dataset, rather than a more complex neural network, delivers the greatest improvements in decoding performance for systems containing up to 161 physical qubits. Quantum error correction (QEC) is a crucial component in the development of fault-tolerant quantum computers, mitigating the effects of decoherence and gate errors that plague quantum information processing. Surface codes are a leading candidate for QEC due to their relatively high threshold for error rates and suitability for implementation on two-dimensional architectures. However, the decoding process, determining the most likely error that occurred given a set of noisy measurements, is computationally intensive. Traditional decoding algorithms, such as minimum-weight perfect matching, struggle to keep pace with the demands of larger quantum systems, creating a bottleneck for scalability. Neural decoders, leveraging the power of machine learning, have emerged as a promising alternative, offering the potential for faster and more efficient decoding.

Appropriate inductive bias within the decoder architecture is essential; generic designs failed to scale effectively, while graph neural networks struggled with the inherent structure of surface codes. A dataset of 107 samples consistently yielded better decoding performance than more complex neural network architectures for surface codes containing up to 161 physical qubits. Standard multilayer perceptrons also failed to scale effectively, and graph neural networks struggled with the inherent structure of surface codes. INT4 quantization, a method of reducing the precision of numerical values, is essential for achieving the necessary sub-microsecond latency when deploying these decoders on field-programmable gate arrays, or FPGAs. The research team evaluated five distinct neural decoder architectures: multilayer perceptrons (MLPs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), graph neural networks (GNNs), and a custom-designed architecture tailored to the surface code structure. MLPs, while simple, lacked the ability to effectively capture the spatial correlations inherent in the surface code. CNNs, commonly used in image processing, also proved inadequate for this task. RNNs, designed for sequential data, struggled with the two-dimensional nature of the surface code. GNNs, which operate directly on graph-structured data, showed initial promise but ultimately failed to scale efficiently. The custom architecture, incorporating specific knowledge of the surface code’s geometry, performed better than generic designs but was still surpassed by a surprisingly simple approach: scaling the training dataset. The team discovered that a dataset comprising 107 samples consistently outperformed more complex architectures, highlighting the importance of data quality and quantity. INT4 quantization reduces the number of bits used to represent each weight and activation in the neural network from the typical 32-bit floating point to just 4 bits. This significantly reduces memory usage and computational requirements, enabling deployment on resource-constrained FPGAs. While this reduction in precision can potentially impact accuracy, the researchers found that it was an acceptable trade-off for achieving the desired sub-microsecond latency. While these findings represent a strong step towards scalable, real-time quantum error correction, sustained logical qubit performance beyond the coherence limits of current superconducting circuits remains elusive; further improvements in physical qubit fidelity are vital.

Data volume surpasses algorithmic complexity in surface code quantum error correction

Neural decoders offer a promising, data-driven route to tackling quantum error correction, and this work subtly shifts the focus from architectural innovation to data management. Surprisingly, simply scaling up training datasets delivers greater performance gains than designing ever-more-complex neural networks, given the current emphasis on algorithmic refinement. However, the work acknowledges a limitation; the benefits were demonstrated specifically for surface codes, raising whether these data-centric improvements will translate to other, more advanced error correction schemes. The traditional approach to improving neural decoders has been to focus on architectural innovations, designing more sophisticated network structures capable of capturing the complex relationships within the error correction code. This research demonstrates that, at least for surface codes, this approach has diminishing returns. The team generated a large dataset of simulated error patterns and used it to train a relatively simple neural network. By systematically increasing the size of the training dataset, they observed a consistent improvement in decoding performance, even without modifying the network architecture. This suggests that the primary bottleneck is not the complexity of the algorithm, but the amount of data available to train it. The surface code, while a leading candidate for QEC, is not without its limitations. Other error correction schemes, such as topological codes with different geometries or codes based on colour codes, may require different decoding strategies and may not benefit from the same data-centric approach.

Given the substantial engineering challenges of building larger and more complex quantum processors, scaling data represents a pragmatic shift rather than algorithms. Identifying readily available techniques like INT4 quantization as important for real-time performance on field-programmable gate arrays (FPGAs) is a significant step towards practical deployment. This data-centric approach enables real-time operation on field-programmable gate arrays and may herald a new era of pragmatic quantum computing development. The use of FPGAs is particularly important for prototyping and testing quantum error correction schemes. FPGAs are reconfigurable hardware devices that allow researchers to implement custom algorithms and architectures without the need for lengthy fabrication processes. This enables rapid iteration and optimisation of decoding algorithms, accelerating the development of practical quantum computers. The ability to achieve sub-microsecond latency on FPGAs is a crucial milestone, as it demonstrates that real-time error correction is within reach. This opens up the possibility of building quantum systems that can operate continuously without being interrupted by long decoding delays.

Examination of neural decoders for quantum error correction demonstrates that prioritising training data volume over architectural complexity is now the most effective path to improved performance. Surface codes, a method of protecting quantum information, benefited from a redesigned approach focusing on scaling data rather than intricate network designs, yielding a functional system deployable on field-programmable gate arrays, or FPGAs, which are specialised electronic chips. Achieving microsecond-scale latency, essential for real-time operation, necessitated the use of INT4 quantization, a data compression technique reducing numerical precision. The implications of this work extend beyond the specific context of surface codes and FPGAs. The finding that data volume is more important than architectural complexity may apply to other areas of quantum computing, such as quantum machine learning and quantum control. This suggests that a shift in focus towards data management and generation could accelerate progress in these fields, potentially leading to the development of more powerful and practical quantum technologies.

Researchers demonstrated that scaling the volume of training data, rather than increasing the complexity of the neural network architecture, improved the performance of quantum error correction decoders for surface codes. This is significant because it provides a practical pathway towards real-time error correction on field-programmable gate arrays, achieving latency within the microsecond timescale with up to 161 physical qubits. The study found that INT4 quantization was necessary to meet these speed requirements. The authors suggest these findings offer concrete guidance for developing scalable and real-time quantum error correction systems.