CEA-Leti Highlights Its Path Towards Full Fault-Tolerant Quantum Computing At IEDM

Cea-Leti Highlights Its Path Towards Full Fault-Tolerant Quantum Computing At Iedm

At the recently concluded IEDM 2022, CEA-Leti presented three papers highlighting its recent successes and upcoming challenges in quantum computing using Si-based qubit devices with FDSOI technology. 

Their plenary paper discussed the approach to scalable quantum computers using silicon technology. A second paper described CEA-Leti’s modelling approach to developing low-temperature FDSOI cryoelectronics. A third invited paper described the institute’s success in developing a strategy for performing electrical characterization at various temperatures, including ultra-low temperatures.

The first paper, “Enabling Full Fault-Tolerant Quantum Computing with Silicon-Based VLSI Technologies,” was presented on December 5 during a plenary session by Maud Vinet, CEA-Leti’s quantum hardware program director. The paper outlines CEA-Leti and CNRS’s proof that FDSOI technology enables complete fault-tolerant quantum computing using very large-scale integration (VLSI) fabrication and design approaches. 

“ quantum technology’s promise to launch a computing revolution reaching unchartered computing territories” is still a far cry because “the path towards full fault-tolerant quantum computing is not yet paved.”

Maud Vinet, now CEO of Siquance (a spin-off from CEA and the French National Centre for Scientific Research (CNRS))

Maud Vinet noted that there is a need for high-quality physical qubits and an effective quantum error correction scheme.

The life-changing applications that the technology promises are a distant goal since the quantum algorithms required to support them require more than 100 flawless qubits to conduct millions of operations. To achieve full computational power of quantum processors, there has to be a way to reduce or eliminate inherent quantum noise, which is the foundation of integrating quantum error correction (QEC) into quantum computation. This led to the development of the fault-tolerant quantum computing (FTQC) framework, which is critical for developing a universal, large-scale quantum computer.

The paper states that topological quantum codes, such as surface codes or triangle color codes, are potential candidates for FTQC. But there are yet challenges to address before QEC can be integrated into real systems.

According to Vinet, full fault-tolerant computing allows for the implementation of algorithms that assume qubits are perfect, which means that these “perfect qubits will be constructed of additional physical qubits to enable quantum error correction.”

Following these early scientific demonstrations, she stated that it is up to electrical engineers and physicists to develop these demonstrations into practical devices. The paper concludes that silicon qubits are a viable candidate for enabling large-scale quantum computing and implementing the algorithms required to generate life-changing applications. 

According to the paper, “It’s now the time for VLSI technologies with more constraints and less versatility but of higher quality, with higher yield and more reproducibility, to address them and provide solutions.”

“FDSOI technology with its backgate provides a way to move the charges away from the interfaces in the qubits on one hand and on the other hand to recenter the Vt of transistors in the control electronics at low temperature. It is thus a unique option to design and fabricate high performance quantum systems-on-chip, (and) CEA-Leti, CEA-IRIG, CNRS Institut Néel and their spin-off, Siquance, are leveraging these FDSOI capabilities to push the quantum computing state-of-the-art in VLSI technologies,” the paper says.

The second paper, Methodology for an Efficient Characterization Flow of Industrial Grade Si-Based Qubit Devices,” tackles the absence of a detailed wafer-level characterization process in the microelectronic industry for devices in their actual operation regime of quantum confinement at low temperatures. To this end, CEA-Leti scientists presented a systematic three-step characterization protocol utilizing up to 300mm automated probers at 300K and 1K.

The three-step characterization protocol includes the following:

  • 300K “transistor-like” metrics informative on material quality and process variability.
  • 1K quantum dot metrics in the many-electron regime. 
  • Qubit metrics at 100mK in the few-electron regime.

To demonstrate the requirement of the three phases, the researchers analyzed the 300K and 1K metrics of spin-qubit devices on 300mm wafers reflecting diverse technical choices for multi-qubit devices.

“This work used for the first time wafer-level quantum dot metrics to evaluate our technology,”


The third paper was titled “FDSOI for cryoCMOS Electronics: Device Characterization Towards Compact Model.” In this paper, they announced their technique for doing electrical characterization at a wide variety of temperatures, including ultra-low temperatures, in this publication, as well as electrical characterization methodologies such as DC, RF, ultra-fast measurements, and high statistics.

The method was applied to FDSOI transistors, proving the technology’s unique cryogenic potential. Extensive analytical models have also been built in the first stages toward a full cryogenic compact model, which will be accessible for designers to optimize their circuits in an industrial platform, i.e., 28nm FDSOI, soon.

According to the paper, many cryogenic applications, such as spatial, high-performance computing, and high-energy physics, have stimulated the exploration of CMOS technology performance at cryogenic temperatures.

Their compact model, unique to each CMOS technology, assures that the circuit operates as intended by the designer. Without compact models, designers must take risks and make decisions about transistor size, polarization, and other parameters that cannot be tested by simulation prior to real circuit production.

Cryoelectronics’ potential uses go beyond quantum computing. High-performance computing can leverage cryogeny to boost processor performance in the 20K-77K range. Improved cryoelectronics can also aid low-temperature sensor electronics for spatial applications, high-energy physics investigations, and other applications.