Welinq is accelerating the development of distributed quantum computing by using NVIDIA CUDA-Q to speed up simulations of detector error models (DEMs). The research team captures how faults trigger error-detection signals and alter logical measurement outcomes within a DEM, then uses the open NVIDIA platform to accelerate sampling from this model.
This advancement builds on a prior circuit-level study of fault-tolerant logical gates across noisy interfaces, reducing the computational cost of evaluating architectural performance. “Combined with decoding, these results constitute an important step for establishing the network requirements and error-correction overhead for reliable distributed quantum computation,” Welinq reports.
Welinq’s Modular Architecture Enables Distributed Quantum Computation
Welinq accelerated simulations of distributed quantum computation by achieving a ten-fold reduction in sampling runtime using NVIDIA CUDA-Q, a platform for accelerating quantum circuit simulations. This speedup centers on detector error model (DEM) sampling, a core step in evaluating the reliability of quantum operations across interconnected processors in modular architectures. The team benchmarked DEM sampling for nonlocal logical CNOT operations implemented through lattice surgery, comparing the CPU-based simulator Stim with the GPU-accelerated CUDA-Q platform.
This advancement allows for larger statistical studies and more precise estimates of logical failure rates, particularly in configurations with multiple interfaces and multi-target logical controlled operations. Being able to rapidly assess these rates is important for benchmarking how internal and interface noise jointly affect encoded operations, informing the choice of error-correcting code families and the allocation of logical qubits across quantum processing units (QPUs).
Welinq’s approach focuses on rotated surface-code patches, implementing distributed logical CNOTs through lattice surgery supported by shared, noisy Bell pairs. The increased simulation speed also enables broader comparisons of patch allocation strategies, examining how assigning control, ancilla and target patches to QPUs affects both interface usage and logical reliability. This builds on the company’s broader vision for quantum-augmented data centers, where QPUs are interconnected through entangled states to execute large-scale quantum algorithms.
Welinq’s development extends beyond simulation, encompassing the modular compiler software araQne, which maps quantum algorithms across networks of interconnected QPUs, and orchestration tools designed to integrate compilation, orchestration and error correction. The ultimate goal is to support reliable distributed execution, addressing the resource and scaling constraints of monolithic quantum architectures.
The team anticipates that this faster sampling will be particularly beneficial for exploring heterogeneous quantum networks, allowing for the assessment of unequal interface quality and platform-dependent QPU noise, provided these characteristics are represented by compatible circuit noise models. The company is building the infrastructure needed to achieve practical distributed quantum computing and integration in quantum-augmented data centers, with the expectation of more extensive architectural comparisons within a given computational budget, Welinq says. The overall runtime improvement, however, remains dependent on decoding and other simulation stages, demonstrating the interconnectedness of optimization efforts in this complex field.
CUDA-Q Accelerates Detector Error Model Sampling with GPUs
The ability to rapidly assess error behavior in interconnected quantum processors received a boost with a ten-fold increase in simulation speed achieved using NVIDIA CUDA-Q, according to recent work by Welinq. This acceleration centers on sampling from a detector error model (DEM), a method for characterizing how faults manifest as altered error-detection signals and impact logical measurement outcomes. By accelerating DEM sampling, researchers can more efficiently evaluate the reliability of quantum operations spanning multiple processors.
This advancement focuses on a specific implementation of error correction using rotated surface-code patches, enabling distributed logical CNOT operations through a process called lattice surgery. The team’s approach extracts a DEM from the physical circuit and its associated noise model, detailing how each error mechanism affects detector readings and logical observable flips.
Generating random realizations of these effects, then decoding them, allows estimation of error correction failure rates at the logical level; faster sampling directly translates to more robust statistical evaluations of architectural performance, according to Welinq. The CUDA-Q implementation on a graphics processing unit (GPU) significantly outperforms the widely used stabilizer circuit simulator, Stim, running on a central processing unit (CPU) in the tested configurations.
“Stim: a fast stabilizer circuit simulator” has long been a standard in the field. But the GPU acceleration allows for larger statistics to be processed within practical computational budgets, supporting systematic exploration of network connectivity, interface quality and error-correction resource allocation. This capability is important for designing quantum data centers where multiple interconnected processors function as a unified, scalable and fault-tolerant computing system.
The DEM describes how physical faults during lattice-surgery CNOT operations, both within the bulk of the quantum processor and along the interfaces connecting them, affect measured error signals and logical observables. Repeating this process across varying code distances and physical noise strengths generates the data needed for creating threshold plots, which map the conditions under which fault-tolerant quantum computation is possible. According to Welinq, fast DEM sampling is essential for obtaining reliable logical-failure estimates. This acceleration supports broader comparisons of interface noise, code distances and quantum processing unit (QPU) allocations.
The team anticipates this will inform the design of future quantum systems, enabling more effective error mitigation strategies and ultimately, more reliable quantum computation. This work, detailed in “Fault-Tolerant Logical Operations and Efficient State Preparation in Modular Quantum Architectures with Noisy Interfaces,” demonstrates a remarkable resilience to interface noise within the configurations and noise model studied.
Circuit-Level Simulations Quantify Inter-QPU Noise in CNOT Gates
Circuit-level simulations now quantify the impact of noise on CNOT gates operating between quantum processing units, revealing that distributed quantum systems can tolerate significantly higher error rates on inter-processor connections than within individual QPUs. This acceleration enables more extensive statistical evaluations of architectural performance, important for designing scalable quantum computers. The team evaluated logical failure probabilities using rotated surface-code patches, encoding logical information across multiple QPUs connected by shared, noisy Bell pairs.
Their analysis assigned enhanced error probabilities to gates operating between processors, representing the additional noise introduced by Bell-pair generation and gate teleportation. Results demonstrate inter-QPU operations can tolerate noise levels up to an order of magnitude larger than those within individual QPUs, with only a minor reduction in the fault-tolerance threshold compared to monolithic designs. This finding challenges previous assumptions about the sensitivity of distributed quantum systems to interface noise.
The team reports, highlighting the importance of efficient simulation techniques. Local two-qubit gates in the simulations were assigned a physical error probability denoted as pbulk, while nonlocal gates received a probability pi equal to α * pbulk. In their experiments, the researchers set α to 20 to model the increased noise associated with inter-QPU communication, compared to α = 1 for all gates within a single QPU.
This setup allowed them to directly compare the fault tolerance of distributed and monolithic architectures under realistic noise conditions. The simulations used LOOM and Stim for circuit-level analysis, with decoding performed using PyMatching. By encoding logical information in rotated surface-code patches and implementing CNOT gates through lattice surgery, the researchers created a realistic model of distributed quantum computation.
Interface Noise Tolerance in Distributed Logical Operations
Accelerated simulations of error behavior are now possible thanks to the application of NVIDIA CUDA-Q, reducing sampling runtime by approximately ten-fold compared to CPU-based methods for certain configurations. Welinq’s work focuses on understanding how errors impact logical operations within distributed quantum architectures, an important step toward realizing quantum-augmented data centers. The DEM is created from noisy circuits implementing lattice surgery, a technique for performing operations through entangled states between quantum processing units (QPUs).
Logical failure probabilities are then evaluated across various code distances and compared to monolithic architectures where α is set to one. This methodology allows for a direct assessment of how well a distributed system can maintain accuracy despite the added noise inherent in inter-QPU communication.
Being able to generate statistical data more quickly has a significant impact on the design process, enabling researchers to evaluate a wider range of network configurations and identify those that support reliable logical operations at a reasonable error-correction cost. This is particularly important for heterogeneous quantum networks where interface quality and QPU noise may vary between platforms.
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