Researchers are now screening oxide semiconductors with thicknesses below one nanometer, a scale rapidly approaching the atomic level, to identify materials suitable for future computer chips. This work focuses specifically on materials for field-effect transistors (FETs) with dimensions below 5nm, as current technology nears the limits of its scaling potential. The team employs a method relying on fundamental physics calculations before physical fabrication to predict promising candidates. According to the research, ultrathin calcium oxide and strontium oxide demonstrate compatibility with p-type device operations and emerge as sub-1-nm-thickness oxide semiconductors capable of simultaneously meeting the high-performance (HP) and low-power (LP) criteria of the International Technology Roadmap of Semiconductors (ITRS) for both n- and p-type devices, potentially broadening the material options for future CMOS technology.
Ab Initio Screening of Sub-1-nm Oxide Semiconductors
Researchers are now evaluating materials with thicknesses measured in fractions of a nanometer, a scale where quantum effects dominate material behavior and manufacturing presents extraordinary hurdles. A team led by Jing Lu at Peking University and Yee Sin Ang at the Singapore University of Technology and Design is employing a computational approach to identify oxide semiconductors thinner than one nanometer for use in next-generation transistors. This work represents a significant step toward building computer chips with dramatically increased density and reduced power consumption. This isn’t simply a search for smaller materials, but a fundamental re-evaluation of what substances can function as semiconductors at such extreme dimensions. The core of their methodology is a process that relies on calculations based on fundamental physics principles before any physical material is created.
This contrasts sharply with traditional materials discovery, which often involves synthesizing and testing numerous compounds in a trial-and-error process; the ab initio approach allows researchers to predict material properties and performance with high accuracy, significantly accelerating the discovery timeline. The team specifically targeted materials suitable for sub-5-nm field-effect transistors (FETs), acknowledging the limitations of current CMOS technology which is rapidly approaching its scaling limits. The researchers state that “ultrathin Ca O 2, CaO, and SrO are compatible with p-type device operations under both high-performance (HP) and low-power (LP) requirements specified by the International Technology Roadmap of Semiconductors (ITRS),” highlighting the potential of these materials to address a critical need in modern chip design. A major challenge in developing oxide semiconductors for CMOS applications has been the prevalence of n-type conductivity, meaning they primarily conduct electrons; complementary circuits require both n-type and p-type materials to function efficiently.
The team’s screening process identified calcium oxide (CaO) and strontium oxide (SrO) as particularly promising candidates for p-type behavior, opening up new possibilities for building fully complementary circuits at the sub-5-nm scale. This dual capability is crucial for achieving both high speed and low power consumption, two key performance metrics for modern electronics. The performance of these ultrathin oxide FETs was also assessed, revealing that they can outperform many existing low-dimensional semiconductors and maintain scalability even below a 5-nm gate length. This suggests that devices built with these materials could potentially push the boundaries of miniaturization even further than currently anticipated. The research, detailed in Phys. Applied, isn’t just about identifying individual materials; it’s about establishing a new paradigm for materials discovery. The team concludes that “Our findings offer an effort in the ab initio, device-driven screening of sub-1-nm-thickness oxide semiconductors, significantly broadening the material candidate pool for future CMOS technology nodes,” suggesting that this computational approach could be applied to identify other novel materials with tailored properties for a wide range of electronic applications.
This proactive, physics-based approach promises to reshape the landscape of semiconductor research and development, paving the way for a new generation of ultra-compact and energy-efficient electronic devices.
