Silicon Qubits Gain Stability with 17 Nanometre Oxide Layer

Arne Loenders and colleagues at Ghent University present a thorough investigation into how gate oxide thickness affects the uniformity of silicon quantum dot arrays. Statistical analysis of 392 quantum dots within a 7×7 array fabricated using a 300mm CMOS-process identified an optimal SiO2 thickness of 17nm, achieving a threshold voltage variability below 63mV standard deviation. The findings offer key design guidance for building dense, scalable silicon spin qubit architectures and highlight the complex interplay between disorder sources and oxide thickness.

Optimised silicon dioxide minimises threshold voltage variation in quantum dot arrays

Threshold voltage variation, a key limitation in scaling silicon quantum dot arrays, has now been reduced to below 63mV standard deviation, a sharp improvement over prior fabrication methods. Previously unattainable uniformity resulted from challenges controlling disorder in dense two-dimensional arrays of these quantum dots, essential building blocks for quantum computers. An ideal thickness of 17nm for the silicon dioxide (SiO2) layer beneath the dots was identified to minimise electrical variations across a 7×7 array of 392 quantum dots. The significance of this reduction stems from the stringent requirements for qubit fidelity; even small variations in threshold voltage translate to differences in qubit frequency and coupling strength, leading to errors in quantum computations. Silicon quantum dots are particularly attractive as qubits due to their long coherence times and compatibility with existing CMOS manufacturing techniques, but realising their potential necessitates precise control over device characteristics.

Capacitances, lever arms, and charging energies were carefully characterised across the 392 quantum dots within the 7×7 array, utilising parallel row-based measurements. This technique allowed efficient data acquisition from multiple dots simultaneously, promising to streamline the fabrication of larger, more stable quantum processors and reduce the complexity of qubit control. The parallel measurement approach significantly reduces the time required for full characterisation compared to sequential probing of individual quantum dots. Capacitance measurements determine the degree of electrostatic confinement of the electron spin, directly impacting qubit frequency. Lever arms, representing the sensitivity of a dot’s energy levels to gate voltages, are crucial for controlling qubit interactions. Charging energies, quantifying the energy required to add an electron to the dot, define the energy scale for qubit operations. Devices fabricated with the 17nm layer exhibited non-monotonic trends, indicating complex interaction between different disorder sources; thinner or thicker layers introduced increased variability in dot characteristics. Extreme ultraviolet (EUV) lithography replaced electron-beam lithography in the fabrication process to improve scalability and precision. EUV lithography offers higher resolution and throughput compared to electron-beam lithography, enabling the creation of denser arrays with improved pattern fidelity, essential for large-scale quantum circuits. Despite this strong advance in uniformity, achieving truly identical qubits and eliminating the impact of charged defects within the SiO2 dielectric remains a significant hurdle to building fully functional, large-scale quantum computers.

Optimal insulating layer thickness balances uniformity and disorder in silicon quantum dots

Silicon quantum dots offer a promising route to scalable quantum computers, yet building arrays where every qubit behaves identically has been notoriously difficult. Researchers have now demonstrated a sweet spot in controlling these tiny structures, identifying 17nm as an optimal thickness for the insulating silicon dioxide layer beneath the dots. This suggests that controlling quantum dots isn’t simply about finding one ideal thickness, but navigating a complex field of competing factors influencing their behaviour. The underlying principle relies on balancing the benefits of increased electrostatic screening provided by a thicker oxide with the increased probability of interface traps and oxide charges that contribute to disorder. These interface traps, located at the SiO2/Si interface, can randomly fluctuate, causing variations in the local electric field and affecting qubit properties. A thinner oxide provides better electrostatic control but exacerbates the impact of these defects. The 17nm thickness appears to represent a compromise, minimising both sources of variability.

Further analysis of the fabrication process revealed that while this thickness minimises electrical variations, competing factors related to disorder within the material introduce complex dependencies. Optimising the insulating silicon dioxide layer beneath silicon quantum dots represents a major advance in controlling these components, essential for building quantum computers. A 17nm thickness minimises variations in electrical properties across dense arrays of these dots, paving the way for more stable and scalable qubit architectures. This is particularly important for implementing error correction schemes, which require many physically identical qubits to encode a single logical qubit. The observed non-monotonic behaviour suggests that the relationship between oxide thickness and disorder is not linear, and that further optimisation may be possible by considering additional parameters such as oxide composition and annealing conditions. This analysis also highlighted that achieving this optimal thickness does not fully resolve the challenge of uniformity, and that further investigation into material disorder is required to improve qubit performance. Future work will likely focus on characterising and mitigating the impact of specific defect types within the SiO2 layer, potentially through advanced materials engineering and surface passivation techniques. Understanding the precise nature of these disorder sources is crucial for achieving the levels of qubit uniformity required for fault-tolerant quantum computation

The research demonstrated that a silicon dioxide layer of 17nm thickness minimises electrical variability in arrays of 392 silicon quantum dots. This optimisation is important because uniform qubit characteristics are essential for building scalable quantum computers and implementing error correction. Researchers found that while oxide thickness impacts qubit properties, competing sources of disorder within the material create complex relationships. The authors intend to further characterise and mitigate specific defects within the silicon dioxide layer to improve qubit performance.