QuEra is co-designing its compiler with quantum hardware to address a surprising inefficiency. The Gidney implementation of Shor’s algorithm spends 99.5% of its qubit-cycles idle, with qubits waiting rather than computing. Yuval Baum of Q-CTRL argues current quantum software design starts “from the top down,” creating theoretical codes and hoping hardware can run them, rather than tailoring software to existing capabilities.
This approach overlooks the critical need for software that can efficiently execute workloads, even as qubit counts rise. Q-CTRL’s Quantum Compiler for Heterogeneous Execution, Scheduling and Synthesis, or Q-CHESS, aims to reduce algorithmic logical error by scheduling algorithms onto user-defined architectures.
Heterogeneous Architecture Reduces Logical Errors in Q-CHESS
The company aims to achieve a 10-6 logical error rate with its Libra system, requiring over 10,000 physical qubits to construct 256 error-corrected logical qubits by 2028; however, QuEra recognizes that qubit count alone does not guarantee functional quantum computation. This inefficiency prompted a shift in focus toward software optimization and architectural design, rather than solely pursuing faster gate speeds.
Proposed answer borrows from classical computing: rather than one uniform sea of identical qubits, a heterogeneous architecture of small, fast QPU modules (each with its own magic state factory, each O(1) in size no matter how large the algorithm grows) connected to a hierarchy of memory, with the weight of scaling carried by memory rather than by compute. Idle logical qubits get moved to slower, cheaper storage instead of being maintained at full speed in the processor.
Idle logical qubits are then moved to slower, less expensive storage, rather than being maintained at full speed within the processor itself; this strategy mirrors techniques used in classical computing to manage resources efficiently. Q-CHESS, the Quantum Compiler for Heterogeneous Execution, Scheduling and Synthesis, results in orders-of-magnitude reduction in algorithmic logical error for the same algorithm, unchanged, simply scheduled onto a better architecture.
The error budget changes as you iterate: idling stops dominating, state transfer across interconnects takes over, and with further tuning you arrive at the regime where you are limited by the T gates you genuinely need.
Q-CTRL’s Compiler Enables Independent Stack Development
QuEra’s compiler stack prioritizes independent development through layered abstraction, allowing quantum error correction experts and hardware engineers to iterate rapidly without dependencies. Stefan Krastanov, leading the quantum error correction layer, explained that this separation isn’t primarily about intellectual property, but an engineering decision designed to accelerate progress on both fronts. The team’s approach allows for a stable interface between layers, enabling parallel development and reducing bottlenecks inherent in tightly coupled systems, QuEra says.
This modular design extends to resource estimation, made possible by parameterizing each compiler step with a machine-readable description of the target architecture. The system is slated for release on Amazon Braket in 2028, with a Next Gen Gigaquop-class system planned for 2028/2029, and the ability to estimate resources before physical construction is a key benefit of this layered approach. Underlying this architecture is Kirin, QuEra’s open-source compiler infrastructure, which is general-purpose and not limited to quantum computing.
This foundation supports the development of a complete stack, including PPVM and Tsim, all of which are available on GitHub. Recognizing the complexity of building a fault-tolerant computer, QuEra recently co-organized the first Workshop on Compilation, Emulation and Verification of Neutral Atom Computing (CEVNAC 2026) alongside IEEE Quantum Week in Toronto, emphasizing the need for collaborative development within the quantum computing community.
Kirin Infrastructure Supports Pre-Build Resource Estimation
Heterogeneous architectures offer a potential solution to the challenge of scaling quantum computation, shifting the burden from compute to memory resources. This contrasts with approaches that attempt to reduce physical qubit counts without considering the impact on runtime, as a reduction to ten thousand physical qubits can result in a 43,000-day execution time for algorithms like Shor’s. The company’s strategy prioritizes a hierarchy of memory connected to these modules, aiming to manage the scaling demands through memory capacity rather than computational power.
Lowering targets within the system focus on embedded controllers and simplifying fundamental operations. A transversal CNOT gate between code blocks, for example, is designed to remain a single, simple operation throughout the entire architecture due to the microarchitecture’s efficiency.
An in-block T gate on a logical qubit expands into resource allocation from a replenished buffer, followed by a permutation of logical qubits and a teleported T gate, further breaking down into gates, measurements and conditional operations. This parameterization also enables resource estimation before the Libra system is physically built, combining coarse operation counting with physical simulations of atomic movements. “The logical error rate is the most accurate resource estimate you can possibly get,” stated a company representative, highlighting the importance of error rates in assessing system viability.
PPVM Models Asynchronous Atom Movement & Failure Modes
Lowering application code into architecture-specific quantum error correction (QEC) gadgets is now managed by a system that treats atom placement like virtual memory, according to colleagues describing QuEra’s approach. This pipeline descends from abstract code to primitive gadgets, accounting for the physical layout of atoms within the trapping hardware and assigning resources without relying on absolute coordinates. Phillip Weinberg argues that simulating a fault-tolerant machine at this scale requires more than simply running a circuit and reading the output, as atom movement, previously considered free, must now be accounted for by QEC.
Some atom moves depend on measurement outcomes, demanding real-time decisions from the processor rather than pre-scheduled actions. The resulting machine operates asynchronously, with atom reloading, decoding and magic state production each running on independent timelines.
Understanding the interactions between the quantum and classical runtime components, the CPU, field-programmable gate arrays, optics, atoms and decoder, is critical, and QuEra’s Pauli Propagation Virtual Machine (PPVM) is the company’s first public tool for modeling this complexity. PPVM combines stabilizer simulation with a model of the interacting runtime and noise sampling that addresses atom-specific failure modes, including single-atom loss during gate operations and correlated loss when qubits are entangled.
Phillip Weinberg, who covered compiler and simulation stack, stated. Kirin, PPVM, and Tsim are all available on GitHub, reflecting QuEra’s commitment to collaborative development, and this collaborative approach acknowledges that no single company can independently develop the necessary tools for a fully functional, scalable quantum computer.
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