CUDA graph optimisation has enabled an RTX 5080 graphics card to now achieve ninety-one percent of the throughput seen on NVIDIA’s GH200 data centre GPU when processing multiple quantum error correction tasks simultaneously, alongside an eight point nine times reduction in decoding latency. The team at KTH Royal Institute of Technology delivered this performance boost by optimising CUDA graphs; employing mixed precision arithmetic with FP16/FP32 formats; using INT8 quantization which halves decoding time for a specific code; and running concurrent decoder instances.

A quantum error correction decoder for NVIDIA graphics cards was engineered, enabling these standard GPUs to achieve ninety-one percent of the performance seen on specialist data centre hardware when tackling multiple tasks simultaneously; decoding latency was also reduced by almost nine times.

This advance uses software improvements that optimise how information is processed within the GPU, including reducing the precision used in calculations without losing accuracy. Quantum error correction is key to building stable quantum computers as it encodes information across physical qubits in a way that protects against errors.

The process involves repeatedly measuring these qubits and using the results, known as syndromes, to infer any corrections needed; this can be likened to gossip spreading through a network where each qubit updates its assessment based on what others report. This advance relies on optimising how calculations are performed within the GPU itself, including streamlining operations with CUDA Graphs, essentially pre-planning steps for complex computations, and reducing calculation precision without sacrificing accuracy.

RTX 5080 achieves near data centre GPU performance via optimised quantum error

An RTX 5080 graphics card now matches ninety-one percent of the throughput achieved by NVIDIA’s GH200 data centre GPU when processing multiple quantum error correction tasks concurrently; decoding latency is also reduced almost ninefold. Software optimizations streamline information handling within the GPU itself to achieve this leap in performance, including reducing calculation precision without sacrificing accuracy, a key step as standard GPUs are increasingly used for complex scientific computing.

Specifically with bivariate bicycle codes at an error probability of 0.003, INT8 quantization halved amortized decoding time compared to independently tuned FP32 calculations on the RTX 5080, while maintaining negligible increases in logical error rate.

Kernel profiling revealed that streaming-multiprocessor and device memory throughput were critical factors during BB90 workload processing. Warp-level collectives, techniques for parallelising operations across processor cores, accelerated QEC by decreasing serial work and increasing scheduler activity, resulting in nearly nine percent faster complete decoder timing without impacting accuracy. Commodity graphics cards demonstrate impressive performance gains; however, validation heavily focuses upon bivariate bicycle codes at a single noise level.

This limited scope raises questions about how well these optimizations translate to other quantum error correction schemes or diverse operating conditions found in real-world devices. The team acknowledges that scaling beyond current problem sizes requires further investigation, vital for future fault-tolerant systems with many qubits, but their findings lack details on precisely *how* decoding time increases as circuit complexity grows. Despite this limited focus, surface, hypergraph product, and bivariate bicycle codes, specific noise levels, and the open question of scalability, this work expands possibilities for building practical quantum computers by proving commodity graphics cards can deliver substantial decoding performance alongside specialised hardware. Their implementation uses CUDA Graphs featuring convergence control, sample retirement, compacted fallback queues, and ordered multi-warp binary elimination. These features enable an RTX 5080 to achieve 91% of a GH200’s highest measured throughput with an 8.9x shorter median submission-to-correction latency, opening a path toward QEC decoder clusters built from commodity GPUs alongside custom control systems.

This research successfully demonstrated that a quantum error correction decoder could be optimized for NVIDIA GPUs using techniques like mixed precision arithmetic and concurrent processing. This implementation achieved 91% of the throughput seen on a GH200 GPU with substantially lower latency, suggesting that readily available hardware can contribute to building scalable quantum computing infrastructure. The authors note further investigation is needed to understand performance as problem sizes increase.

👉 More information
🗞 Engineering Low-Latency, High-Throughput Quantum Decoders on NVIDIA GPUs
✍️ Stefano Markidis and Luca Pennati (Ivy Peng
KTH Royal Institute); Ivy Peng (Affiliation: KTH Royal Institute of Technology)
🧠 ArXiv: https://arxiv.org/abs/2610.28867

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