KAIST chip adjusts processing speed for faster AI tasks

KAIST researchers have developed a new semiconductor device, the programmable dynamic memtransistor (PDM), capable of adjusting its processing speed to better handle real-time artificial intelligence tasks. The technology, led by Chair Professor Shinhyun Choi, achieved up to a 40-fold reduction in prediction errors for time-varying data compared to conventional devices.

This innovation combines memory and computing functions within a single device, allowing it to retain programmed settings without continuous power. Professor Choi explained, “This study demonstrates an AI semiconductor whose response characteristics can be programmed to efficiently process data changing at different speeds.” The PDM is expected to improve performance in applications like autonomous vehicles and wearable devices.

Dual-Layer PDM Design Enables Adjustable Response Speeds

The ability to tune a semiconductor’s response speed represents a significant leap forward in artificial intelligence hardware, and a team at KAIST has demonstrated this with a new device architecture. Unlike conventional transistors with fixed operational speeds, the programmable dynamic memtransistor (PDM) allows for adjustments after fabrication, offering a level of flexibility previously unattainable in semiconductor design. This innovation stems from a dual-layer structure within the transistor itself, strategically combining charge storage for data processing with an electron trapping layer that governs response speed.

The nonvolatile control offered by the electron trapping layer allows the PDM to maintain programmed response characteristics without continuous power input. Incoming data is processed within the charge storage layer, while the trapping layer modulates the recovery time, the speed at which the semiconductor returns to its original state, across multiple levels.

Experiments conducted by the KAIST team revealed a tuning range of approximately five-fold for current recovery time and more than ten-fold for characteristic frequency, demonstrating substantial control over the device’s temporal behavior. This precise modulation is critical for efficiently handling data streams with varying speeds, a common challenge in real-world applications. The implications of this adjustable response are particularly pronounced when analyzing time-varying data, as evidenced by the team’s experiments predicting complex datasets.

The team successfully fabricated an integrated PDM array and validated its performance by predicting complex data, achieving accuracy comparable to software-based systems while significantly reducing energy consumption. This energy efficiency is a key benefit, particularly for portable devices and applications where power constraints are paramount, and the PDM’s compatibility with existing commercial semiconductor manufacturing processes further enhances its appeal.

Beyond reduced power consumption, the PDM’s ability to adapt to different input timescales eliminates the need for complex preprocessing of data, streamlining the overall system architecture. Conventional systems often require software to prepare data before it can be processed by hardware, adding computational overhead and latency. The PDM, by contrast, can directly handle data streams with varying speeds, simplifying the design and improving real-time performance.

This is especially crucial for applications demanding immediate responses, such as autonomous vehicles and robotics. Chair Professor Choi anticipates that the PDM will become a core technology for improving the performance of AI devices, including autonomous vehicles, robots, and wearable technology, while simultaneously reducing their power demands.

The research, led by Dae-won Kim of the KAIST Graduate School of Semiconductor Technology, involved contributions from Yoonho Cho, Seokho Seo, Yujin Kim, See-On Park, Taehwan Jang, and Chaebin Park, as well as Young Taek Oh and Jae-Duk Lee from Samsung Electronics’ Semiconductor R&D Center. The findings were published in Nature Communications on July 4, supported by funding from the National R&D Program, the ETRI R&D Support Program, the HRD Program for Industrial Innovation, Samsung Electronics, and other sources.

This study demonstrates an AI semiconductor whose response characteristics can be programmed to efficiently process data changing at different speeds.

Chair Professor Choi, KAIST
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Ivy Delaney

Ivy Delaney has been working with neural networks and machine learning since the mid-nineties, back when a couple of hidden layers and a long afternoon of training counted as ambitious. She has watched the field go from academic curiosity to the thing quietly running underneath everything, and she brings that long view to quantum computing. For Quantum Zeitgeist she covers the ground where the two fields meet. That means quantum machine learning and the variational algorithms it leans on, and it also means the less glamorous but more interesting story of classical machine learning already doing real work inside quantum machines, decoding error-correcting codes, calibrating noisy hardware and learning the error models that simulators depend on. She writes about the hardware those algorithms have to run on too, and about the post-quantum cryptography scramble that the same hardware has set off. Her stories typically start with the paper, whether that is peer-reviewed work, conference proceedings or an arXiv preprint, with the source linked so you can hold a claim up against the research it came from. She is unimpressed by benchmarks that will not say what they beat, and by demonstrations that only work in the press release.

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