IBM has unveiled a semiconductor advance with the first chip built at the 0.7 nanometer, or 7 angstrom, node, marking the first time transistors have been scaled below 1nm and challenging the limits of traditional chip manufacturing. The new chip packs nearly 100 billion transistors onto a fingernail-sized area, nearly twice the density of IBM’s previous 2nm chip. Technical results reported by the company project up to 50 percent more performance, or 70 percent greater energy efficiency, compared to its 2nm node chips, benefiting applications like generative AI and cloud infrastructure. “IBM’s latest chip advance marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.”
7nm Nanostack Architecture Enables Sub-1nm Transistor Design
The unveiling of a 0.7 nm chip packs nearly 100 billion transistors onto a chip the size of a fingernail, nearly twice the density of IBM’s 2 nm chip. This achievement isn’t simply a reduction in size; it’s a reimagining of chip construction, enabled by a novel three-dimensional nanostack architecture. Unlike current nanosheet technology, IBM’s design vertically stacks and staggers transistors, maximizing density and allowing for varied material combinations within each layer to optimize performance and power efficiency independently. Experimental validation, detailed in research presented at VLSI, confirms the nanostack technology can be physically built and supports functional computation; the architecture provides 40 percent scaling in SRAM, crucial for high-bandwidth data demands of advanced artificial intelligence workloads. According to IBM, this breakthrough unlocks the potential for at least a decade of future scaling on the semiconductor roadmap, extending logic technology into the angstrom-level where dimensions approach the size of individual atoms.
IBM’s 2nm to 0.7nm Scaling Demonstrates 40% SRAM Improvement
Beyond shrinking transistor size, IBM’s advancements in chip architecture are yielding quantifiable improvements in performance and efficiency. Research detailed at the VLSI symposium demonstrates a 40 percent scaling in static random-access memory, or SRAM, using the new nanostack design. This increase in SRAM efficiency is critical as designers strive to create chips capable of handling the escalating data demands of advanced artificial intelligence applications. The innovative three-dimensional approach, termed “nanostack,” allows for the utilization of diverse material combinations within each layer, independently optimizing the performance and power consumption of individual transistors. Experimental validation, including functional CMOS inverter operation, confirms the nanostack technology is not merely theoretical but demonstrably capable of supporting real computation. The implications extend beyond immediate performance gains; IBM projects that this architecture will enable at least another decade of scaling, pushing the boundaries of what’s physically possible in chip design.
While transistor nodes increasingly represent a generation of manufacturing technology rather than a precise physical dimension, IBM’s 0.7 nm technology, also referred to as 7 angstroms, proves continued scaling remains achievable, offering a pathway to future innovation.
High NA EUV Lithography Supports Future Semiconductor Roadmap
Researchers at IBM are actively preparing for the next wave of semiconductor manufacturing, leveraging High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography to support their recently unveiled 0.7 nanometer node technology. This advanced lithography, provided by ASML, enables the ultra-precise circuit printing necessary for creating the smaller, more powerful chips at the atomic scale, and work is being done at IBM’s semiconductor research facility in Albany, New York. The facility isn’t working in isolation; collaborations with partners like Lam Research Corp., Tokyo Electron, and SCREEN Semiconductor Solutions have already yielded functional devices utilizing these new processes and tools. The development of nanostack architecture, IBM’s first known three-dimensional, nanosheet-based design, is intrinsically linked to the success of High NA EUV. The company’s commitment extends to establishing Anderon, a dedicated quantum foundry, drawing on IBM’s expertise in both quantum computing and semiconductor manufacturing to bolster domestic production of quantum wafers.
With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.
Jay Gambetta, Director of IBM Research and IBM Fellow
