Researchers at the University of Southern California and the Universidad Autonoma de Madrid have demonstrated anisotropic scaling of a surface-code quantum memory on IBM’s Heron-generation superconducting processors. The team moved beyond uniform scaling to achieve codes with distances of (3,5) and (5,3), improving the protection of logical quantum states.
This work addresses a central challenge in quantum computing: implementing error correction on hardware where the physical qubit layout doesn’t naturally match the code’s requirements, using a “fold-unfold” embedding and robust dynamical decoupling. The results establish a path toward testing subthreshold surface-code scaling with optimized control on non-native architectures.
Surface Code Scaling on Heavy-Hex Processors
Achieving subthreshold scaling of quantum memory represents a pivotal challenge, particularly when the hardware’s inherent connectivity doesn’t align with the demands of the surface code. Researchers have now addressed this issue using IBM’s heavy-hex superconducting processors, employing a co-designed approach to both code embedding and control mechanisms. This strategy centers on a “fold-unfold” embedding, minimizing circuit depth via SWAP gates and utilizing bridge ancillas, coupled with robust, gap-aware dynamical decoupling (DD).
Experiments conducted on Heron-generation devices perform anisotropic scaling from a uniform distance 3 code to anisotropic distance (d_x,d_z) = (3,5) and (5,3) codes. The team found that increasing (d_x) improves the protection of Z-basis (X-basis) logical states across multiple quantum error correction cycles. While global subthreshold scaling for all initial logical states remains elusive, the results suggest it is attainable with further hardware refinements.
Dynamical decoupling suppresses coherent ZZ crosstalk and non-Markovian dephasing that accumulate during idle periods inherent in heavy-hex layouts. The researchers found that DD also eliminates misleading subthreshold claims that can arise when comparing scaled codes lacking DD to smaller codes employing it.
To quantify performance, they derived an entanglement fidelity metric that is computed from X- and Z-basis logical-error data, providing per-cycle bounds accounting for state preparation and measurement (SPAM) errors. As the paper states, “The entanglement fidelity metric reveals that widely used single-parameter fits used to compute suppression factors can mischaracterize or obscure code performance when their assumptions are violated.”
Researchers are tackling a persistent hurdle in quantum computing: maintaining coherence during error correction on hardware not ideally suited to the task. Their recent work focuses on IBM’s heavy-hex superconducting processors, where qubit connectivity presents challenges for implementing surface codes. The team’s approach centers on a co-designed system integrating a “fold-unfold” embedding strategy with robust dynamical decoupling (DD). This embedding minimizes circuit depth by utilizing strategically placed bridge ancillas to facilitate qubit communication on the heavy-hex lattice.
Importantly, the researchers found that DD suppresses coherent ZZ crosstalk and non-Markovian dephasing that accumulate during idle gaps on heavy-hex layouts. To rigorously quantify performance, the team derived an entanglement fidelity metric that is computed directly from X- and Z-basis logical-error data and provides per-cycle, SPAM-aware bounds. The results suggest that achieving global subthreshold scaling is within reach, contingent upon minor hardware improvements and continued optimization of control techniques like DD.
Progress toward practical quantum computing hinges on effectively correcting the errors inherent in fragile qubits, and recent work demonstrates a refined method for evaluating the performance of quantum error correction (QEC) schemes on IBM’s heavy-hex superconducting processors. Beyond simply scaling up code size, researchers are now focusing on precisely how that scaling impacts error rates, and a newly developed entanglement fidelity metric offers a more accurate assessment than previously used techniques.
A key challenge lies in accurately quantifying performance when dealing with complex noise environments. Dynamical decoupling (DD) suppresses coherent ZZ crosstalk and non-Markovian dephasing that accumulate during idle gaps on heavy-hex layouts.
Conventional assessments of quantum error correction often rely on single-parameter fits to quantify how effectively errors are suppressed as code size increases, but recent work reveals these methods can be misleading. The team’s analysis, conducted on IBM’s Heron-generation devices, highlights critical assumptions underpinning these fits: stationarity, unitality, and negligible logical SPAM errors. They found these conditions do not consistently hold true in their experimental data.
Specifically, the study demonstrates that applying these standard fits can mask genuine improvements in error correction, or even falsely suggest subthreshold scaling where none exists. This is particularly relevant for architectures like IBM’s heavy-hex processors, which require SWAP gates to implement surface codes. This new metric offers a more robust way to evaluate performance, moving beyond the limitations of relying on simplified suppression factors. Ultimately, the work underscores the importance of rigorous performance quantification in the pursuit of practical quantum computing.
Recent advances in quantum error correction have focused on scaling up surface codes, but a significant hurdle remains: implementing these codes on hardware with connectivity that doesn’t naturally align with the code’s structure. This work co-designs both the code embedding and control mechanisms to overcome this challenge. The team employed a depth-minimizing SWAP-based “fold-unfold” embedding utilizing bridge ancillas, alongside robust dynamical decoupling (DD).
On Heron-generation devices they perform anisotropic scaling from a uniform distance 3 code to anisotropic distance codes of (3,5) and (5,3), meaning the code’s protection against errors varies depending on the quantum state being protected. They found that increasing (d_x) improves the protection of Z-basis (X-basis) logical states across multiple quantum error correction cycles.
Recent progress in quantum error correction increasingly focuses on adapting surface codes to existing hardware architectures, even when native qubit connectivity doesn’t perfectly align with the code’s requirements. This technique co-designs the code embedding with the control mechanisms, allowing for efficient implementation despite the non-ideal hardware. On Heron-generation devices they performed anisotropic scaling from a uniform distance 3 code to anisotropic distance (d_x,d_z) = (3,5) and (5,3) codes, finding that increasing (d_x) improves the protection of Z-basis (X-basis) logical states across multiple quantum error correction cycles.
Crucially, the researchers integrated robust dynamical decoupling (DD) with this embedding strategy. While full subthreshold scaling remains a goal, the results suggest it is within reach with minor hardware improvements, establishing a concrete path to robust tests of subthreshold surface-code scaling and demonstrating a tailored approach to error mitigation.
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