Researchers from HSE MIEM and Samara University have created LRF-3D, a new algorithm that enhances processor reliability by automatically bypassing faulty nodes within three-dimensional networks-on-chip. The system employs a hierarchy of eight local algorithms to address “dead ends” caused by manufacturing defects or crystal degradation in the on-chip network, a common issue for data centers and supercomputers.
Aleksandr Romanov, Leading Research Fellow at HSE MIEM, explains that the algorithm works much like a car navigation system, finding an alternative route if a familiar one is blocked. Testing across 36 scenarios demonstrates LRF-3D achieves a path length deviation of only 1.64% from a reference algorithm, even with up to 50% of nodes failing.
LRF-3D Algorithm Bypasses Faulty Nodes in 3D Networks-on-Chip
Developed by researchers at HSE MIEM and Samara University, LRF-3D addresses a critical challenge in modern chip design: maintaining functionality despite manufacturing defects or the gradual degradation of silicon crystals. These imperfections create “dead ends” within the intricate on-chip communication network, potentially halting data flow and compromising performance in data centers, supercomputers, and artificial intelligence systems.
The LRF-3D system distinguishes itself through a hierarchical structure comprised of eight local algorithms, each designed to navigate around these faulty nodes without requiring a complete map of the network. The researchers validated LRF-3D’s performance across 36 scenarios, including mazes, corridors, and various failure patterns.
Testing revealed substantial improvements over existing routing methods; with a 13-30% node failure rate, LRF-3D successfully delivered data packets in 86% of attempts. The algorithm’s speed surpasses that of established alternatives, making routing decisions 16.7 times faster than the A* algorithm and 22.5 times faster than LOFT, HSE MIEM says. The team reports that LRF-3D outperforms LOFT by a factor of more than 137 in terms of route quality.
Romanov anticipates future work will focus on real-world chip testing to evaluate power consumption and data transfer rates, and suggests that if the results are confirmed, the technology could help create a new generation of multiprocessor systems-on-chip that operate more reliably, even under challenging conditions. The study received support from the Russian Science Foundation, and the findings are published in IEEE Access.
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