Researchers at the Beijing Academy of Quantum Information Sciences have demonstrated a new method for resetting superconducting qubits in just 48 nanoseconds. This rapid reset relies on dedicated dissipation units integrated directly onto the quantum processor, isolating qubits from external noise sources. The work achieves residual excited-state populations of 0.29% and 0.67% after a 400-nanosecond pulse, and efficiently removes leakage from the |f⟩ state, establishing a scalable approach to dissipation engineering. This on-chip dissipation offers a simpler architecture for quantum state initialization and error correction.

On-Chip Dissipation Architecture for Rapid Qubit Reset

A median reset time constant of approximately 48 nanoseconds for the transition was achieved using a new on-chip dissipation architecture, demonstrating a significant acceleration in qubit initialization speeds. The design intentionally balances rapid qubit relaxation during reset with minimized Purcell decay during standard quantum operations, a critical factor for maintaining coherence. This approach differs from conventional qubit reset protocols that often depend on external circuitry, which can introduce thermal noise and complicate scaling. The researchers report an effective bath temperature of 30 mK for the reset process, indicating a highly controlled thermal environment.

Analysis of reset decay times revealed differing characteristics potentially linked to fabrication variations in coupling capacitance or systematic uncertainties during parameter extraction. Specifically, qubit dephasing, occurring at a rate of 100 MHz, slows qubit decay, while residual flux-pulse distortions, despite infinite impulse response (IIR) correction, may influence extracted parameters and the observed reset dynamics. These pulse distortions could also affect short-time population dynamics, potentially biasing fitted values and contributing to discrepancies between measured and model-predicted reset times.

The processor used in this work contains 72 qubits arranged in a staggered layout, each labeled according to its reset line and position on that line. Measurements combined data from 20 analyzed qubits across seven lines, with preparation, reset and readout performed in groups to minimize crosstalk.

The reset waveform itself consists of cosine falling and rising edges flanking a constant-frequency plateau, each edge lasting one nanosecond and the illustrative waveform used a 10-nanosecond plateau duration. Sweeping the plateau frequency and duration generated reset maps, enabling precise control over the qubit state. Extraction of experimental parameters relied on fitting an exponential function to the observed reset behavior, with an offset fixed during the process.

Fitting for both g and $κ_{r}$ in log $T_{1}$ yielded median values of 5.5 MHz and 11.0 MHz, respectively, with a measured reset-lifetime median of 48.1 nanoseconds. The observed reset speed is further supported by single-shot characterization of qubit reset, demonstrating clear I-Q distributions and projected histograms for qubits prepared in both |g⟩ and |e⟩ states.

These distributions, obtained both with and without the 400-nanosecond reset pulse, visually confirm the effectiveness of the on-chip dissipation method. The processor’s architecture, with its integrated dissipation units, provides Purcell protection while isolating qubits from external thermal noise, contributing to the observed high fidelity and speed.

Resistive Load Design and Dissipator Coupling

Simulations and analysis revealing a relationship between resistance and dissipator decay rate demonstrate how the design of on-chip resistive loads directly influences the speed of qubit reset. The extracted qubit-dissipator coupling strengths and dissipator decay rates have medians of g/2π = 5.5 MHz and $κ_{r} / 2 π$ = 11.0 MHz, respectively. The median extracted coupling strength is lower than the design value of 8.5 MHz, which corresponds to a qubit-dissipator coupling capacitance of $C_{q r}$ = 1.2 fF.

The researchers detail how the dissipator decay rate is directly linked to the load admittance, referred to the dissipator voltage antinode, and the equivalent capacitance at that plane. This careful calibration of capacitive and mutual-inductive coupling optimizes the reset process. The underlying concept is simple. Each qubit is coupled to a dedicated dissipative resonator, which provides a pathway for qubit excitations to be absorbed by an on-chip resistive load.

The qubit frequency $ω_{q}$ , dissipator frequency $ω_{r}$ , coupling strength g and dissipator decay rate $κ_{r}$ are designed to enable rapid qubit relaxation when resonant with the dissipator while suppressing Purcell decay during off-resonant coherent operations. The dissipator frequencies have a median of $ω_{r} / 2 π$ = 3.724 GHz, while the median idle and maximum qubit frequencies are and, respectively. This precise control over the dissipator’s characteristics is essential for achieving the desired reset performance and minimizing unwanted interactions with the qubits.

Purcell Protection and Effective Bath Temperature

Instead, the system uses on-chip dissipation to isolate qubits and establish a stable, low-temperature operating point. Finite-element electromagnetic simulations validated a lumped-element model, revealing how mutual coupling influences the dissipator’s performance. Specifically, the simulations extract a load admittance at the dissipator port, influencing the equivalent capacitance and ultimately the decay rate of the system. This precise relationship allows for fine-tuning of the reset process, optimizing the balance between rapid dissipation and minimal disturbance to qubit coherence.

This is achieved through careful design of the dissipator’s characteristics, ensuring that unwanted population transfers are minimized. Evaluating reset efficiency across multiple qubits yielded a median of 99.28%, confirming the broad applicability of the on-chip dissipation scheme. The analytical and numerical solutions demonstrate coherent exchange oscillations, with the decay scale determined by $e^{- κ_q(0)t}$ , where $κ_{q} (0)$ is half the dissipator decay rate.

Leakage Removal from the |f⟩ Qubit State

The architecture’s effectiveness extends to managing qubit states beyond simple ground and excited levels. The team specifically targeted the |f⟩ state, a source of error in quantum computations. Applying the 400-nanosecond pulse reduced the probability of a qubit remaining in the |f⟩ state from 77.54% to 0.51%, as determined through single-shot readout analysis. Accompanying this reduction was an increase in the probability of the qubit relaxing to the |g⟩ state, rising from 3.52% to 18.36% after the pulse, indicating efficient population transfer.

Scalable Reset Implementation for Superconducting Qubits

This rapid reset occurs with an effective bath temperature of 30 millikelvin, a critical parameter for maintaining qubit coherence during complex calculations. The architecture isolates qubits from external thermal noise by integrating dissipation units directly onto the quantum processor, a departure from conventional methods reliant on external circuitry. These figures represent an improvement in qubit state control, minimizing errors that could accumulate during extended computations.

The design’s scalability stems from the use of dedicated dissipation units comprising resonators coupled to on-chip resistive loads, a configuration that provides Purcell protection. This protection minimizes unwanted electromagnetic interactions, further enhancing qubit coherence. The architecture’s simplicity also suggests potential for broader adoption and integration into existing quantum computing platforms, offering a practical solution for improving qubit initialization and error correction.

👉 More information
🗞 Implementing rapid reset of superconducting qubits with on-chip dissipation
✍️ Feiyu Li et al. (1)
🧠 ArXiv: https://arxiv.org/abs/2611.14391v1

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