Rigetti and Goldman Sachs have been researching ways to make quantum error-correcting more efficient. On Nov 11, 2022, they published their results on arXiv. In the paper, the researchers suggest a new design technique for adapting large-scale superconducting quantum computers for error correction, which would speed up the development of fault-tolerant quantum computing applications.
Various quantum computer manufacturers, including Rigetti, have spent the last several years customizing concepts for near-term quantum computers to accomplish specific jobs in fields such as machine learning, optimization, and simulation.
While Rigetti believes that quantum advantage will be attained before fault tolerant systems are built, a subset of applications will necessitate fault tolerance and hence error correction techniques. Quantum error correction techniques are a set of methods used to correct errors in quantum computers.
They protect quantum information against decoherence and other sources of error and are a critical component of quantum computing, cryptography, and fault-tolerant communication.
In the study, Rigetti and Goldman Sachs outline how they approach design optimization for contemporary gate-model superconducting processors, such as those built by Rigetti.
They presented a new type of gate with the potential to simplify system calibration and enhance the threshold of the surface codes. These new Hardware Optimized Parity (HOP) gates are intended to be parallel interactions between fine-tuned superconducting transmon qubits.
Their superconducting processor architecture is based on planar transmons stacked in a square array, with one qubit connected to four nearest neighbors through adjustable couplers, and it is a leading design for near-term processors.
The team feels that the accompanying improvements to error correction thresholds are a clear indication that this hardware tailoring technique may become an important part of system design in the future.