Quantum Circuits Become 14 Per Cent More Reliable with New Method

Scientists at Keio University and Routin have developed a new framework employing the Digital Annealer (DA) to prioritise accuracy in quantum circuit transpilation, achieving significant reductions in CNOT gate counts. Kazuma Watanabe and colleagues demonstrate a hybrid approach yielding an average CNOT reduction of 13.7% compared to standard optimisation techniques, particularly benefiting structured circuits. The Full DA method surpasses ISAAQ by 23.1% on average. This work highlights a key “time-for-quality” trade-off, suggesting that DA-assisted global optimisation can enhance the usability of current quantum hardware for high-precision applications where minimising gate noise is vital.

Significant CNOT gate reductions via accuracy-prioritised quantum circuit optimisation

A maximum CNOT gate reduction of 57.4% on structured quantum circuits has been achieved, representing a substantial improvement over existing optimisation techniques. Previously, compilers favoured compilation latency over minimising gate errors, struggling to deliver gains without prohibitive computational cost; this new threshold surpasses the limitations of prior “accuracy-first” transpilation methods. The new framework utilises the Digital Annealer (DA), a specialised computer designed for solving complex combinatorial optimisation problems, and prioritises accuracy by translating circuit optimisation into a Quadratic Unconstrained Binary Optimisation (QUBO) format. This transformation allows the DA to perform global optimisation, exploring a wider solution space than traditional heuristic methods. The QUBO formulation represents the circuit’s connectivity and gate dependencies as a mathematical function, where the objective is to minimise the number of CNOT gates while satisfying the circuit’s logical requirements.

Benchmarks reveal the Hybrid approach outperforms Qiskit’s highest optimisation level by an average of 13.7%, while the Full DA method exceeds ISAAQ by 23.1% on average, demonstrating a practical “time-for-quality” trade-off for near-term quantum hardware. The Hybrid approach, combining the Digital Annealer (DA) with Qiskit routing, achieved an average CNOT gate reduction of 13.7% compared to Qiskit’s highest optimisation level, particularly on circuits with specific structures like GHZ and ASP designs where initial qubit placement is critical. These structured circuits benefit from the DA’s ability to find globally optimal mappings, assigning logical qubits to physical qubits in a way that minimises the required CNOT gates. Solving both mapping and routing using the DA, the Full DA method matched the Hybrid approach on these structured circuits. Furthermore, it reduced CNOT gates by an average of 23.1% over ISAAQ, peaking at a 90.8% reduction. However, performance diminished on circuits with random connections, highlighting a trade-off between optimisation problem size and solution quality. The ISAAQ algorithm, a commonly used transpilation method, serves as a baseline for comparison, demonstrating the substantial gains achieved by the DA-based approaches. The 90.8% reduction observed in specific instances indicates the potential for dramatic improvements in circuit fidelity for carefully designed quantum algorithms.

Optimising quantum circuits reveals trade-offs between structure and performance

Many researchers aim to build practical quantum computers, but current machines are hampered by errors and limited qubit numbers. The Noisy Intermediate-Scale Quantum (NISQ) era is characterised by these limitations, necessitating innovative approaches to maximise the performance of available hardware. This work offers a way to squeeze more performance from existing hardware by carefully optimising the instructions sent to the processor, specifically reducing the number of complex CNOT gates. CNOT gates, while essential for creating entanglement, are also among the most error-prone operations on current quantum devices. Minimising their count directly translates to a reduction in overall circuit error rates and improved computational reliability. The ‘Full DA’ approach, while powerful on certain circuit designs, falters when faced with more chaotic, randomly connected systems, suggesting a fundamental tension between the complexity of the optimisation problem and the ability to find genuinely superior solutions. This suggests that the effectiveness of global optimisation techniques like those employing the DA is heavily dependent on the underlying structure of the quantum circuit.

Reducing the number of CNOT gates directly tackles a major source of error in current, noisy quantum processors, as this operation is fundamental to quantum computing. Accepting increased computational effort for improved accuracy, this ‘time-for-quality’ trade-off, is a valuable contribution to making near-term quantum hardware more useful for practical applications. The computational cost associated with DA-based optimisation is higher than that of heuristic methods, but the resulting reduction in CNOT gates can outweigh this cost by improving the overall fidelity of the quantum computation. Initial qubit mapping optimisation, even with added computational effort, can yield significant reductions in error-causing CNOT gates and will likely begin to shape future compilation strategies. A method for prioritising accuracy in quantum circuit design through the use of the Digital Annealer, a specialised computer adept at solving complex optimisation problems, is now established. By translating circuit optimisation into a mathematical format suitable for the DA, gate fidelity increased five-fold while minimising error-inducing CNOT gates, though performance varied with more complex designs, suggesting circuit topology significantly influences optimisation effectiveness. This five-fold increase in gate fidelity represents a substantial improvement in the reliability of quantum operations and opens up possibilities for more complex and accurate quantum computations. Further research will focus on developing hybrid algorithms that combine the strengths of DA-based global optimisation with the efficiency of heuristic methods, tailoring the optimisation strategy to the specific structure of the quantum circuit.

The research demonstrated an average reduction of 13.7% in CNOT gate counts using a new optimisation framework leveraging the Digital Annealer. This matters because fewer CNOT gates directly translate to reduced errors in near-term quantum computers, improving the reliability of calculations. The study highlights a trade-off between computational effort and solution quality, with performance dependent on circuit structure. Authors intend to develop hybrid algorithms combining the Digital Annealer with existing methods to further refine optimisation strategies for different quantum circuits.