IBM’s 7 Angstrom Chips Boost Efficiency by 70% Over 2nm

IBM has unveiled a computer chip built with transistor nodes measuring 0.7 nanometers, or 7 angstroms. In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors, a significantly higher density than current 2 nanometer node chips. To illustrate the scale, IBM notes a human red blood cell is approximately 10,000 times larger than a single node on the new chip. These 7 angstrom chips are reportedly 70% more efficient, or 50% more powerful, than their 2 nanometer predecessors, potentially delivering seven times more performance, around 7,000 TOPS.

IBM Achieves 7 Angstrom: First Sub-1nm Node Chips

These chips are not simply smaller versions of existing technology; they represent the first transistors measured at less than one nanometer, utilizing nodes just 0.7 nanometers wide. The team at IBM accomplished this through innovations in wafer bonding, SRAM scaling, and channel material science, building upon years of research into chip architecture. This miniaturization dramatically increases performance and efficiency. In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors.

IBM claims these new chips are 70% more efficient, or 50% more powerful, than their previous 2 nanometer node chips. The team notes that widespread adoption of 2 nm devices will likely occur closer to the end of the decade, followed by 1.4 nm and 1nm devices. The foundation for this breakthrough lies in a new architecture dubbed “nanostack,” a departure from traditional two-dimensional scaling. Instead of solely reducing transistor size laterally, the team explored stacking them vertically, effectively adding a third dimension. This approach, developed over the last few years, involved bonding two wafers to create a multilayered structure, a process refined to minimize defects and ensure precise alignment. The nanostack design also allows for independent optimization of both NFET and PFET channels within each node, further enhancing performance and enabling even smaller nodes in the future.

Nanostack Architecture Enables 3D Transistor Density

The drive to increase transistor density has led IBM researchers beyond conventional two-dimensional scaling, resulting in the nanostack architecture. Building upon prior work with nanosheets, which underpinned the development of 3nm and 2nm chips, the team began exploring the potential of adding a third dimension to transistor design. This exploration stemmed from a desire to increase transistor density within a fixed area, prompting consideration of what could be achieved by building “taller” rather than simply “smaller” transistors. The resulting 7 angstrom chip utilizes this nanostack device architecture, a design the team believes will sustain silicon innovation for at least another decade. A key breakthrough enabling this density was a new technique in thin dielectric wafer bonding, allowing the creation of a multilayered structure with minimal defects and precise alignment. This process yields a true 3D transistor, demonstrably extendable and scalable for future processor generations.

By stacking transistors, the team could also independently optimize materials used in each node’s channels, maximizing performance. This staggered design for field-effect transistors improves cell designs and suggests a pathway toward even smaller nodes. Both NFET and PFET channels are optimized within a “gate stack” solution, allowing independent performance of each. The team managed to scale up static random-access memory (SRAM) by 40% in the 7 angstrom design, a substantial leap in memory capacity unseen in over a decade. Researchers stated that this nanostack architecture could power multiple generations of transformative devices.

7 Angstrom Chips Deliver 70% Efficiency Gains

The pursuit of miniaturization at IBM has yielded a chip boasting transistor nodes measuring just 0.7 nanometers, or 7 angstroms, a significant leap beyond the current 2-nanometer standard. In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors. These new IBM sub-1nm chips are 70% more efficient, or 50% more powerful, than the 2 nanometer node chips. If 7 angstrom chips were used to train today’s massive, frontier-model LLMs, we could drastically cut training time from around three months to a couple of weeks. The result is a true 3D transistor design, optimized for performance and scalability, and capable of leveraging new materials for enhanced efficiency.

Wafer Bonding and SRAM Scaling Innovations

The pursuit of miniaturization in chip technology has yielded a significant advancement with the development of 7 angstrom node chips, representing a leap beyond the current 2nm standard and promising substantial gains in performance and efficiency. Central to this achievement are innovations in wafer bonding and static random-access memory (SRAM) scaling, allowing for unprecedented transistor density. In a 7 angstrom chip the size of a fingernail, there are roughly 100 billion transistors. This approach enabled a doubling of transistor density compared to 2nm chips, paving the way for more powerful and energy-efficient computing. Beyond simply shrinking existing components, the new architecture leverages thin dielectric wafer bonding to stack transistors vertically, exploring the third dimension to overcome the limitations of two-dimensional scaling. This nanostack design not only increases transistor density but also allows for the independent optimization of materials within each node, maximizing performance.

A particularly notable advancement is the 40% increase in SRAM capacity achieved within the 7 angstrom design. These new IBM sub-1nm chips are 70% more efficient, or 50% more powerful, than the 2 nanometer node chips. The team can leverage new materials for the channels in each node with the stacked transistors, maximizing the performance of each independently.