Riverlane has patented a method to improve the bandwidth between classical computing interfaces and quantum processing units (QPUs) in quantum computers. The technique compresses digital control signals and splits them into sub-streams, which are transmitted to the QPU in a staggered configuration. This reduces error rates and power consumption, enabling the development of scalable, fault-tolerant quantum computers with thousands of qubits. The invention also minimises the power demands of extreme refrigeration required to maintain QPUs at low temperatures.
The race to make quantum computers useful is accelerating, with new technology designed and built to work together across an integrated quantum stack. Modern quantum computers combine classical computing hardware with a quantum processing unit (QPU) that uses qubits for advanced computing capabilities. However, a bandwidth problem between the classical and quantum systems worsens as the number of qubits increases. Qubits are also delicate and prone to data errors due to external interference, requiring extremely low temperatures to minimize noise. A new invention provides high bandwidth rates while minimizing power demands for refrigeration.
“Our invention provides the high bandwidth rates required as quantum computers scale while minimising the huge power demands imposed by such extreme refrigeration requirements.”
Quantum Computers: The Hybrid System
Quantum computers are a combination of classical computing hardware, which powers high-performance computers (HPC), and a quantum processing unit (QPU) that utilises qubits to give the computer its unique capabilities. The classical interface instructs the QPU with a continuous stream of instructions to perform operations that keep the QPU functioning. However, there is a bandwidth problem between the classical and quantum systems due to the limited, fixed number of wires connecting the QPU to the classical interface.
Challenges in Scaling Quantum Computers
As quantum computers scale up to tens, hundreds, and thousands of qubits to unlock their true potential, the bandwidth problem between classical and quantum systems worsens. Additionally, qubits are delicate and highly susceptible to data errors caused by external interference or “noise.” To minimise noise, most types of qubits require the QPU to be kept at extremely low temperatures, often just a few millikelvins above absolute zero.
A New Invention to Address Bandwidth and Power Constraints
A recent invention provides the high bandwidth rates required for scaling quantum computers while minimising the significant power demands imposed by extreme refrigeration requirements. The patent covers a method for transmitting control signals from a classical computing interface to a QPU. This method involves compressing digital control signals at the classical interface and splitting the compressed control signals into sub-streams, which are then transmitted to the QPU in a staggered configuration.
Benefits of the Staggered Configuration
The staggered configuration used to transmit sub-streams allows control signals to be transmitted to the QPU in a way that respects power constraints and minimises error rates. This, in turn, facilitates the development of scalable, fault-tolerant universal quantum computers with thousands or more physical qubits. Additionally, the staggered configuration reduces crosstalk on communication channels between the classical interface and the QPU, thereby reducing error rates and power consumption.
Riverlane’s Role in Quantum Computing Advancements
This invention is a significant achievement for Riverlane and its IP team, confirming their position at the forefront of quantum computing. The technology and its implications for the wider product portfolio and future plans can be further explored by contacting the company.
Executive Summary
Riverlane has patented a method for transmitting control signals between classical computing interfaces and quantum processing units (QPUs), which minimises power consumption and error rates. The invention enables high bandwidth rates and reduces power demands for extreme refrigeration requirements, facilitating the development of scalable, fault-tolerant quantum computers with thousands of qubits.
- Quantum computers require a combination of classical computing hardware and a quantum processing unit (QPU) utilising qubits.
- There is a bandwidth problem between classical and quantum systems as the number of qubits increases.
- Qubits are delicate and susceptible to data errors due to external interference (‘noise’), requiring extreme refrigeration to minimise noise.
- Riverlane has patented a method for transmitting control signals from a classical computing interface to a QPU, improving bandwidth rates and reducing power demands.
- The method involves compressing digital control signals, splitting them into sub-streams, and transmitting them to the QPU in a staggered configuration.
- This staggered configuration reduces crosstalk, error rates, and power consumption, facilitating the development of scalable, fault-tolerant quantum computers with thousands of qubits.