Quantum Speed Limit’s Role in Advancing Efficiency of Quantum Computing Platforms

The Quantum Speed Limit (QSL) is a key concept in quantum computing, indicating the minimum time required to complete a task. It influences the feasibility of quantum circuits and is particularly relevant in the current noisy intermediate-scale quantum (NISQ) era, characterized by imperfect qubit control. Researchers from the Institute for Theoretical Physics University of Innsbruck and Parity Quantum Computing GmbH have studied the QSL of quantum gates for two major quantum computing platforms, neutral atoms and superconducting circuits. Their findings could help improve the efficiency of quantum computing platforms and advance the field beyond the NISQ era.

What is the Quantum Speed Limit and Why is it Important?

The Quantum Speed Limit (QSL) is a fundamental concept in quantum computing that denotes the shortest time needed to accomplish a given task. It is dependent on the system under consideration, its Hamiltonian, and the control knobs available to steer the dynamics. The QSL is crucial in the field of quantum computing as it impacts the experimental feasibility of quantum circuits. Algorithms with circuit depths that significantly exceed the error time scales will result in faulty quantum states, necessitating error correction.

The QSL is particularly important in the current era of quantum computing, known as the noisy intermediate-scale quantum (NISQ) era. This period is characterized by imperfect qubit control and qubit numbers that prohibit quantum error correction for relevant problem sizes. Despite these challenges, recent proof-of-principle experiments have demonstrated that a computational quantum advantage over classical computers can be reached with NISQ hardware. However, it remains a significant challenge to go beyond the proof-of-principle stage and demonstrate a quantum advantage for practically relevant computational tasks on resource-limited present-day devices.

To reach a practical quantum advantage regime in NISQ-era digital quantum computing, it is of crucial importance to execute quantum algorithms as efficiently as possible. This means minimizing the quantum algorithm run times and gate counts, a task that can be addressed in various ways. One option is to find an algorithm’s optimal circuit representation, requiring a minimal circuit depth together with a minimal gate count for a given set of available gates. Another option is to minimize the time for each elemental quantum gate of a given quantum circuit.

How Can We Determine the Quantum Speed Limit?

Determining the QSL of quantum gates for major quantum computing platforms is a complex task. The study conducted by Daniel Basilewitsch, Clemens Dlaska, and Wolfgang Lechner from the Institute for Theoretical Physics University of Innsbruck and Parity Quantum Computing GmbH focused on two major quantum computing platforms that allow for two-dimensional (2D) qubit arrangements – neutral atoms and superconducting circuits.

The researchers’ study reveals how close the current experimental gate protocols are in comparison to their QSLs, providing an indication of what can theoretically still be gained from further speeding up gate protocols. Moreover, provided that every gate could be experimentally realized at the QSL, their analysis gives an estimate of how many gates can be executed realistically before decoherence takes over and renders longer quantum circuits practically infeasible.

To this end, the researchers considered two prototypical quantum computing algorithms: the quantum Fourier transform (QFT) required for Shor’s algorithm for integer factorization, and the quantum approximate optimization algorithm (QAOA) used to solve combinatorial optimization problems. Considering standard NISQ devices for both neutral atoms and superconducting circuits with qubits arranged in a 2D grid architecture with only nearest-neighbor connectivity, they calculated the circuit run times with gates at the QSL for both algorithms.

What are the Challenges and Solutions in Determining the Quantum Speed Limit?

A common challenge arising in 2D platforms with nearest-neighbor connectivity is the requirement to perform gates between non-neighboring qubits. In the standard gate model (SGM), such gates can be replaced by sequences of universal single and two-qubit gates using the available local connectivity. However, this comes at the price of increasing the circuit depths and gate counts.

As an alternative to the SGM, the researchers also examined circuit representations using the so-called parity mapping (PM). In brevity, the PM for quantum computing and quantum optimization is a problem-independent hardware blueprint that only requires nearest-neighbor connectivity at the cost of increased qubit numbers.

What are the Findings and Implications of the Study?

The researchers found that neutral atom and superconducting qubit platforms show comparable weighted circuit QSLs with respect to the system size. This finding allows for a direct comparison of both platforms in terms of the maximal problem sizes that should currently be feasible on their NISQ representatives.

The study’s findings have significant implications for the field of quantum computing. By determining the QSLs for individual gates and using them to quantify the circuit QSL of the quantum Fourier transform and the quantum approximate optimization algorithm, the researchers have provided valuable insights into the potential for improving the efficiency and effectiveness of quantum computing platforms. This could ultimately help to advance the field beyond the current NISQ era and towards the realization of practical quantum advantage.