Intel’s quantum computing researchers, Samuel Neyens and Otto Zietz, have developed a process to collect high-volume data on the performance of spin qubit devices. The process demonstrates high uniformity and fidelity, with single-electron devices achieving 99.9% fidelity. This development moves silicon-based quantum computers closer to commercial production. Intel is also working on building fault-tolerant quantum computers by improving qubit density, uniformity, and measurement statistics. The company’s testing process is fully automated, speeding up data collection. The cryogenic wafer prober, used in the process, was developed in collaboration with Bluefors and AEM Afore.
Intel’s Advancements in Quantum Computing
Quantum computing research engineers at Intel Foundry Technology Research have made significant strides in the development of spin qubit devices. They have developed a 300-millimeter (mm) cryogenic probing process that collects high-volume data on the performance of these devices across full wafers. The results of this process have demonstrated impressive uniformity, fidelity, and measurement statistics of spin qubits.
The researchers also found that single-electron devices from these wafers perform well when operated as spin qubits, achieving 99.9% fidelity for qubits fabricated using complementary metal oxide semiconductor (CMOS) manufacturing. This high device yield, combined with cryoprober testing, provides a straightforward path from device fabrication to the study of spin qubits, eliminating failures due to yield or electrostatics at the dilution refrigerator stage.
Intel’s Approach to Building Fault-Tolerant Quantum Computers
Intel is making progress towards building fault-tolerant quantum computers by focusing on three factors: qubit density, reproducibility of uniform qubits, and measurement statistics from high volume testing. Firstly, Intel’s silicon spin qubits are smaller and denser than other qubit types such as superconducting and trapped ion qubits, enabling more spin qubits on a chip. The company’s extreme ultraviolet (EUV) lithography helps achieve this density in combination with high volume on devices.
Secondly, creating quantum computers with millions of uniform qubits requires highly reproducible and reliable fabrication. Spin qubits leverage Intel’s 300-mm CMOS manufacturing techniques, which routinely produce billions of transistors per chip. Lastly, the development of large-scale quantum computers in the CMOS manufacturing space requires a high-volume 300-mm cryogenic probing system for fast process iteration and learning. Intel’s entire testing process, from alignment to device measurement, is fully automated and programmable, speeding up device data collection by several orders of magnitude compared with the measurement of singular devices in a cryostat.
Cryogenic Probing Process and Spin Qubits
For spin qubits, wafer-scale probing requires further cooling hardware to reach the required temperatures lower than 4 kelvin (K). The cryogenic wafer prober, developed in collaboration with Intel, is manufactured by Bluefors and AEM Afore. The cryoprober can load and cool 300-mm wafers to a base temperature of 1 K at the chuck and an electron temperature of approximately 1.6 K in roughly two hours. After cooldown, thousands of spin qubit arrays and test structures on the wafer are available for measurement.
Spin qubits based on electrons in silicon have shown impressive control fidelities but have historically been challenged by yield and process variation. To achieve high yield, researchers used a combination of processes from industrial transistor manufacturing. The quantum dots are defined by a planar architecture. Active gates, used for controlled accumulation, are defined in a single layer. In later devices, a second passive layer for screening/depletion is also integrated. The gate electrodes are isolated from the heterostructure by a high-dielectric-constant composite stack (high-K stack) while neighboring gates are isolated by a spacer stack.
Process Optimization and Qubit Yield
To improve device variation and performance, researchers use two approaches – reducing fixed charge in the high-K stack and optimizing the gate layer architecture. Fixed charge in the high-K stack can arise based on the materials and conditions of the deposition, as well as through exposure to subsequent processing. Fixed charge can be reduced in the devices by limiting the temperature of the spacer process to within the typical thermal budget for back-end-of-line (BEOL) processing. These reductions in fixed charge led to reduced crystallization of the high-K stack at lower temperatures.
Improving qubit yield is a necessary part of scaling up quantum processors, as larger systems will depend on an increasing number of qubit components to function. To analyze the yield of this fabrication flow, researchers tested 12-quantum-dot (12QD) devices across a wafer and calculated component yield for ohmic contacts, gates, quantum dots, and full 12QD devices. This testing method provided fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to low process variation and high yield commensurate with the yield in a leading edge technology node.
Future of Spin Qubit Devices
High-volume testing with the cryoprober will continue to enable process optimization to reduce variation and disorder, as well as more advanced performance screening (such as charge noise, interdot coupling, and single electron transition disorder) to identify the leading-edge test chips for quantum computing applications. These results set a new standard for the scale and reliability of spin qubit devices today, paving the way for much larger and more complex spin qubit arrays of the future.
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