UK-based quantum engineering company, Riverlane, has developed the world’s first dedicated decoder chip for quantum computing. The chip, known as DD0A, is part of Riverlane’s Quantum Error Correction Stack, a technology that aims to reduce error rates in quantum computers. The company has also made its intellectual property for the next-generation decoder available to other quantum computer manufacturers. Riverlane’s CEO, Steve Brierley, stated that the decoder chip is a significant step towards scaling quantum computing operations. The company plans to demonstrate the decoder in live hardware in late 2023.
Quantum Engineering Company Develops First Dedicated Decoder Chip
Cambridge-based quantum engineering company, Riverlane, has developed the first dedicated decoder chip specifically for quantum computing. This development is part of the company’s ongoing efforts to construct a Quantum Error Correction Stack, a necessary component for every quantum computer to achieve a useful scale. The decoder chip, known as an application-specific integrated circuit (ASIC), is a crucial part of this stack and is the first of its kind to be fabricated.
Riverlane has also made public the intellectual property (IP) for its next generation decoder, allowing any quantum computer manufacturer to utilise it in their own hardware. The company plans to demonstrate this decoder in live hardware in the fourth quarter of 2023.
The Importance of Quantum Error Correction
Quantum error correction is a significant challenge for quantum computers. It is the process that allows for the production of a large-scale quantum computer with error rates low enough to perform useful calculations. To achieve this, a dedicated Quantum Error Correction Stack is needed, which sits between the quantum hardware and application layers. Every useful quantum computer, regardless of its qubit type and application, will require a Quantum Error Correction Stack.
Riverlane is developing both the decoders and control systems that together transform many unreliable physical qubits into one more reliable ‘logical’ qubit. Quantum decoders must manage the terabytes of data produced by quantum computers every second to prevent errors from propagating and rendering calculations useless.
The ASIC Chip and Its Role
The ASIC chip, named DD0A, is the first release in the Decode ASIC Family. It delivers a high-speed, high-capacity and cost-effective decoder capable of operating at high volumes with significantly reduced power consumption. The Decode ASIC Family and Decode IP Family can be integrated into superconducting, trapped ion and neutral atom quantum hardware.
The Decode IP Family and Its Function
Riverlane has also launched its Decode IP Family, which delivers real-time processing for error correction during runtime. It operates with unprecedented speed and accuracy. The Decode IP Family is designed to be used with Field Programmable Gate Arrays (FPGAs), which allow for quick prototyping and integration, accelerating the speed of innovation.
Future Developments and Plans
Riverlane will continue to develop and validate its next generations of its Decode ASIC Family and Decode IP Family as it progresses along the company’s roadmap. The company is now implementing quantum algorithms on actual hardware and has found a balance to address all the metrics required to create a real-world decoder to solve real-world problems.
“Steve Brierley, CEO and founder of Riverlane, explained: “We’re entering a new era of quantum computing where we begin tackling the technology’s defining challenge – the need to scale from a few hundred quantum operations to a trillion quantum operations without failure. The only way to achieve this is via a complex new technology called quantum error correction. Riverlane is developing comprehensive technology to accelerate this transition for all quantum computers. Our launch of the world’s most powerful quantum decoder and the first ever decoding chip today are important steps in that journey.”
Brierley added: “We are now implementing quantum algorithms on actual hardware. Crucially, Riverlane has found a balance to address all the metrics required to create a real-world decoder to solve real-world problems – making our decoder the most powerful decoder available.”
Quick Summary
UK-based company Riverlane has developed the first dedicated decoder chip for quantum computing, a critical component in the Quantum Error Correction Stack needed for large-scale, useful quantum computations. The company has also made its intellectual property for the next generation decoder available to other quantum computer manufacturers, with plans to demonstrate this technology in live hardware by the end of 2023.
- UK-based quantum engineering company, Riverlane, has developed the world’s first dedicated decoder chip for quantum computing.
- The company has also published its decoder intellectual property (IP) and roadmap for early error-corrected quantum computing.
- The decoder chip, known as the application-specific integrated circuit (ASIC) demonstrator, is a key part of the Quantum Error Correction Stack, which is necessary for every quantum computer to achieve useful scale.
- Riverlane plans to demonstrate this decoder in live hardware in Q4 2023.
- Quantum error correction is a significant challenge for quantum computers, as it allows for the production of a large-scale quantum computer with low enough error rates for useful calculations.
- Riverlane is also developing the control systems that, along with the decoders, form the Quantum Error Correction Stack.
- The ASIC chip, named DD0A, is the first in the Decode ASIC Family, which provides a high-speed, high-capacity, and cost-effective decoder.
- Riverlane’s CEO and founder, Steve Brierley, stated that the company is developing technology to accelerate the transition to quantum error correction for all quantum computers.
- Riverlane has also launched its Decode IP Family, which offers real-time processing for error correction during runtime.
- Both the Decode ASIC Family and Decode IP Family can be integrated into various types of quantum hardware.