Cryogenic Circuits Overcome Valley Splitting to Boost Qubit Coherence

A new framework integrating valley maps with cryogenic circuit simulations overcomes challenges of spatially varying valley splitting and stringent power constraints. Pau Dietz Romero of University of Cologne, and colleagues, have developed a fully integrated cryogenic signal generator and a noise-aware optimisation procedure. This achieves an average shuttling fidelity of 99.99 ±0.007% at an average velocity of 20m/s over 10μm, with power consumption in the tens of μW. The results validate the practical application of on-chip control settings to mitigate valley disorder and improve scalability in future quantum architectures.

On-chip circuitry enables record fidelity quantum information transfer over silicon

A shuttling fidelity of 99.99 ±0.007% has been achieved, representing a substantial improvement over previous demonstrations of 99.7% and 99.54% accuracy. This level of precision is a vital threshold for scalable quantum computation, as even minor errors accumulate and disrupt complex calculations. Quantum error correction, a crucial component of fault-tolerant quantum computing, demands exceedingly low error rates to function effectively; this new result brings the field closer to that requirement. Previously, maintaining such high fidelity over ten micrometres proved impossible due to variations in ‘valley splitting’ within the silicon material. UNSW Sydney scientists overcame this limitation by integrating a custom-designed circuit directly into the cryogenic environment, enabling on-chip storage and replay of optimised control signals.

The new approach minimises power consumption to the tens of μW while simultaneously mitigating the effects of material imperfections, paving the way for stronger and more scalable quantum processors. The stringent power constraints are particularly important for cryogenic systems, where cooling capacity is limited, and excessive heat dissipation can compromise qubit coherence. An average shuttling fidelity of 99.99 ±0.007% was achieved over a ten micrometre distance, utilising a velocity of 20 metres per second. This performance was validated through a co-simulation framework combining realistic valley maps with detailed cryogenic circuit simulations including electronic noise. These valley maps, generated through characterisation of the silicon material, reveal the spatial distribution of valley splitting, allowing the control signals to be pre-compensated for these variations. The team’s integration of a custom-designed circuit into the cryogenic environment allows for on-chip storage and replay of optimised control signals, reducing active analogue power consumption to the tens of μW. Velocity modulation, shaping waveforms period by period through discrete resistor settings, avoids the need for high-resolution digital-to-analogue converters typically found in quantum systems. These converters are often a significant source of noise and power consumption. Furthermore, the system demonstrates durability to spatially varying ‘valley splitting’, the energy difference between electron states, within the silicon material, a common source of error in these architectures. Valley splitting arises from the quantum confinement of electrons in silicon nanowires, and its spatial variation is due to imperfections in the nanowire geometry and material composition.

Electron shuttling, the technique employed here, involves the transfer of quantum information encoded in the spin of an electron between distant qubit locations. This is achieved by manipulating the electron’s valley index, a degree of freedom related to the shape of its energy bands. By precisely controlling the electric fields applied to the silicon nanowire, the electron’s valley state can be manipulated, effectively ‘shuttling’ the quantum information. The 10μm distance achieved in this work represents a significant step towards building larger, more complex quantum circuits. Maintaining high fidelity over this distance is crucial for enabling long-range interactions between qubits, which are essential for implementing complex quantum algorithms. The use of Si/SiGe heterostructures further complicates the process, as strain induced in the material also affects valley splitting. The co-simulation framework accounts for these effects, providing a more accurate model of the system’s behaviour.

Mitigating valley disorder improves silicon qubit coherence for longer distance quantum computation

UNSW Sydney scientists are edging closer to scalable quantum computers by refining how quantum information is moved within silicon chips. This latest work addresses the problem of ‘valley splitting’, imperfections in the silicon material that disrupt the delicate quantum states of qubits during transit. The current co-simulation framework, however, presents a challenge to further development. Achieving 99.99% fidelity over ten micrometres does not immediately translate to a fully scalable processor; maintaining such precision across millimetre or centimetre-scale chips remains a significant hurdle. The primary challenge lies in the accumulation of errors over longer distances and the increasing complexity of controlling the electric fields required for shuttling. Furthermore, the fabrication of silicon nanowires with uniform properties over such lengths is a significant technological challenge.

Nevertheless, this work establishes a key foundation by demonstrating a practical method for mitigating valley disorder, a key source of qubit instability in silicon. This development provides a method for precisely controlling the movement of quantum information within silicon chips, overcoming challenges posed by imperfections in the material itself. ‘Valley splitting’, a variation in electron behaviour, previously hindered reliable data transfer. Researchers at UNSW Sydney enabled on-chip storage and reuse of optimised control signals by integrating a custom-designed circuit directly into cryogenic systems, minimising power consumption while maintaining high fidelity. This approach raises questions regarding scalability; extending these results to longer distances and more complex qubit arrangements will be vital for building practical quantum computers. Future research will focus on developing more sophisticated control algorithms and fabrication techniques to address these challenges. The ability to dynamically compensate for valley splitting in real-time, rather than relying on pre-characterised valley maps, could further improve the robustness of the system. Exploring alternative materials and device architectures may also offer pathways to overcome the limitations of current silicon-based qubits. The implications of this work extend beyond silicon qubits; the principles of noise-aware optimisation and on-chip control could be applied to other types of quantum systems, such as superconducting qubits and trapped ions.

The research successfully demonstrated high-fidelity electron shuttling over a distance of 10μm in silicon, achieving an average fidelity of 99.99 ±0.007% at an average velocity of 20m/s. This is important because it addresses the problem of signal degradation caused by imperfections in silicon materials, which previously limited the reliable transfer of quantum information. By integrating a custom circuit for on-chip control and optimising signals to compensate for material variations, researchers maintained low power consumption during the process. The authors intend to develop more sophisticated control algorithms and fabrication techniques to further improve the system’s robustness and scalability.