New Chip Cuts Power Use for Post-Quantum Security

Wireless medical devices, including critical implants like pacemakers and insulin pumps, are now potentially shielded from future quantum computing attacks thanks to a new microchip developed at MIT. Researchers have created an ultra-efficient design that brings computationally demanding post-quantum cryptography techniques to energy-constrained edge devices previously unable to support them; the chip is comparable in size to a fine needle tip. This innovation addresses a growing vulnerability as quantum computers advance and threaten to break current data security schemes. “Tiny edge devices are everywhere, and biomedical devices are often the most vulnerable attack targets because power constraints prevent them from having the most advanced levels of security,” says Seoyoon Jang, lead author of the research and an MIT electrical engineering and computer science graduate student. “We’ve demonstrated a very practical hardware solution to secure the privacy of patients.”

Quantum Threats Drive Post-Quantum Cryptography Development

The escalating threat of quantum computing is driving the development of specialized hardware to safeguard sensitive data, particularly within vulnerable edge devices. Researchers at MIT have engineered an ultra-efficient microchip designed to implement post-quantum cryptography techniques on wireless biomedical devices, such as pacemakers and insulin pumps, which traditionally lack the power reserves for such computationally intensive security measures. These devices, often considered prime targets for malicious actors, are now receiving a focused defense against future attacks capable of breaking current encryption standards. The impetus for this development stems from the anticipated ability of quantum computers to compromise established security schemes; agencies like the National Institute of Standards and Technology (NIST) are preparing to phase out traditional cryptography in favor of more robust post-quantum cryptography (PQC) algorithms.

Recognizing the urgency, the MIT team created an application-specific integrated circuit (ASIC), a chip roughly the size of a fine needle tip, that dramatically reduces energy consumption while maintaining a high level of security. This chip incorporates multiple layers of protection, including two distinct PQC schemes for redundancy and an on-chip random number generator to enhance security and efficiency; the design also addresses physical hacking attempts like power side-channel attacks. Compared to existing methods, the new technology achieves over ten times improvement in energy efficiency, enabling secure wireless medical devices and a wider range of resource-constrained applications like industrial sensors and smart tags. “As we transition into post-quantum approaches, providing strong security for even the most resource-limited devices is essential,” explains Anantha Chandrakasan, MIT provost.

Custom ASIC Design Minimizes Energy Consumption

The proliferation of connected devices has created a paradox: while enhancing functionality, it simultaneously expands the attack surface for malicious actors, particularly as the threat from quantum computing becomes more real. Existing security protocols, once considered robust, are increasingly vulnerable to decryption by sufficiently powerful quantum computers, necessitating a shift towards post-quantum cryptography (PQC). However, implementing these computationally intensive algorithms presents a significant challenge for energy-constrained edge devices, those tiny, battery-powered systems embedded in everyday objects. Wearable, ingestible, and implantable devices lacked the power reserves to run PQC effectively until now. This innovation isn’t merely about bolstering security; it’s about enabling it where it was previously impractical. According to the research team, the new technology is more than ten times more energy-efficient than prior designs.

On-Chip Randomness & Side-Channel Attack Protections

Researchers at MIT have engineered a microchip prioritizing security for a growing class of vulnerable devices, focusing on protections beyond standard encryption methods. Unlike previous designs, this application-specific integrated circuit (ASIC) incorporates multiple layers of defense, including an on-chip true random number generator, a critical component for generating secure keys used in post-quantum cryptography (PQC). “PQC is very secure algorithmically, but making a device resilient against physical attacks usually requires additional countermeasures that increase energy consumption at least two or three times.” The team deliberately avoided simply increasing computational power, instead focusing on efficiency gains through shared resources and targeted countermeasures. Recognizing that power side-channel attacks, where hackers analyze a device’s energy consumption to steal data, pose a significant risk, they implemented redundancy only in the most vulnerable parts of the PQC protocols. An early fault-detection mechanism halts operations if a voltage glitch is detected, a common issue in wireless biomedical devices with unstable power supplies. “At the end of the day, because of the techniques we utilized, we can apply these post-quantum cryptography primitives while adding nothing to the overhead, with the added benefit of robustness to side-channel attacks,” Jang states. Testing revealed the chip achieved between 20 to 60 times higher energy efficiency compared to other PQC security techniques, a crucial advancement for devices like pacemakers and insulin pumps previously unable to support such demanding protocols.

Researchers at MIT have created an ultra-efficient application-specific integrated circuit (ASIC) capable of running computationally intensive post-quantum cryptography (PQC) protocols on devices previously too power-constrained to implement them. A significant challenge overcome by the team was the substantial increase in power consumption typically associated with PQC, often two or three times higher than existing methods.