Quantum Computer Design Uses ‘cat States’ to Correct Errors Reliably

Felix Tripier and colleagues present a blueprint for a fault-tolerant quantum computer utilising trapped ions. The new architecture, termed the ‘walking cat’ approach, incorporates a compiler, error-correction protocols based on low-density parity-check (LDPC) codes, and a micro-architecture designed for efficient operation. The design achieves the potential to execute approximately one million T gates per day with 2,514 physical qubits, encoding 110 logical qubits, and simulations suggest it could perform quantum Hamiltonian simulations of a 100-site Heisenberg model within a month using 10,000 physical qubits. By prioritising simplicity and utilising experimentally demonstrated hardware components, the design indicates that a fault-tolerant quantum computer with hundreds of logical qubits capable of running millions of logical gates is achievable soon, enabling exploration of classically intractable physics simulations.

Trapped-ion architecture surpasses one million daily T gates with 110 logical qubits

A dense architecture design achieves 110 logical qubits executing approximately one million T gates per day using 2,514 physical qubits. This represents a substantial increase from previous designs, which were often limited to theoretical models lacking detailed implementation plans or suffered from impractical resource requirements. The ability to perform one million T gates per day is a crucial metric in quantum computation, as T gates are a universal gate set component, meaning any quantum algorithm can be decomposed into a sequence of these gates. Crossing this vital threshold enables exploration of classically intractable physics simulations, previously beyond reach due to the scale of required computation. The new ‘walking cat’ architecture, for trapped-ion devices, integrates a complete blueprint encompassing a compiler, error-correction protocols utilising low-density parity-check (LDPC) codes, and detailed simulations; it prioritises simplicity and experimentally demonstrated hardware. Trapped-ion technology is favoured due to the long coherence times and high fidelity of operations achievable with individual ions, making them suitable for building stable qubits.

Simulations indicate the architecture could model a 100-site Heisenberg model within a month, demonstrating a pathway towards practical, fault-tolerant quantum computation with hundreds of stable, logical qubits. The Heisenberg model is a fundamental model in quantum magnetism, used to describe the interactions between spins in a material. Simulating such systems classically becomes exponentially difficult as the number of sites increases, making quantum computers a potentially powerful tool for materials science. A novel ‘cat factory’ is incorporated into the system, producing specialised quantum states distributed throughout the device to enable logical operations, all underpinned by LDPC codes for error correction. These ‘cat states’, specifically superpositions of coherent states, are robust against certain types of errors and are central to the architecture’s fault tolerance. Modelling complex physics problems, such as the 100-site Heisenberg model, is achievable within one month, highlighting a pathway towards simulating systems intractable for conventional computers. Increasing feasibility is achieved by prioritising experimentally demonstrated hardware components, though these figures do not yet account for the significant engineering challenges of scaling up to thousands of qubits while maintaining coherence and control. The LDPC codes employed are chosen for their efficient decoding properties, crucial for real-time error correction in a large-scale quantum computer.

Scaling challenges and fidelity limitations in large qubit ‘cat state’ production

Despite this detailed architectural proposal, the practical implementation of the ‘cat factory’ remains a significant hurdle. These specialised quantum states, essential for logical operations, require precise control and manipulation of individual ions. Generating high-fidelity cat states necessitates carefully calibrated laser pulses and precise control of the ion’s motional state within the trap. The work acknowledges reliance on hardware already demonstrated on small devices, but scaling this up to thousands of qubits introduces considerable complexity. Maintaining the coherence of these states becomes increasingly difficult as the number of qubits increases, due to interactions with the environment and imperfections in the control systems. The fidelity of producing and maintaining these cat states at scale is not explored in detail, potentially limiting achievable error rates and ultimate computational power. Specifically, imperfections in the cat state preparation and measurement processes will contribute to logical errors, impacting the overall performance of the quantum computer.

The proposed architecture’s compiler plays a vital role in translating high-level quantum algorithms into a sequence of operations executable on the physical qubits, optimising for gate count and minimising the impact of errors. The micro-architecture is designed to facilitate efficient communication and entanglement between qubits, crucial for performing complex quantum computations. This detailed architecture establishes a pathway towards building a practical, fault-tolerant quantum computer using trapped ions. The design prioritises simplicity and utilises components already demonstrated in smaller experiments, suggesting near-term feasibility for a machine with hundreds of stable, logical qubits capable of performing millions of operations. Crucially, the architecture’s foundation in low-density parity-check codes and the use of ‘cat states’ to perform logical operations represents a significant advance in quantum information processing, offering a concrete, fully simulated design that moves beyond theoretical possibilities. The use of 2,514 physical qubits to encode 110 logical qubits highlights the overhead associated with quantum error correction, a necessary step to overcome the inherent fragility of quantum information. Further research will focus on optimising the cat state production process, improving the efficiency of the LDPC decoder, and addressing the engineering challenges of scaling up the system to a larger number of qubits, ultimately paving the way for practical quantum computation.

The potential impact of such a machine extends beyond physics simulations. Applications in materials discovery, drug design, and financial modelling could all benefit from the ability to solve problems currently intractable for classical computers. However, realising this potential requires overcoming significant technological hurdles and demonstrating sustained, reliable operation of a large-scale, fault-tolerant quantum computer.

The researchers developed a fault-tolerant quantum computer architecture for trapped-ion devices, termed the walking cat architecture, which utilises low-density parity-check codes and ‘cat states’. This design encodes 110 logical qubits using 2,514 physical qubits and is capable of executing approximately one million T gates per day. Simulations suggest a 100-site Heisenberg model could be simulated within a month using 10,000 physical qubits, potentially allowing exploration of classically intractable physics. The authors intend to optimise cat state production and the LDPC decoder as next steps in development.