Scientists Develop Fault-Tolerant Quantum Circuit Embedding Technique

Scientists have made a breakthrough in quantum computing, developing a protocol that enables fault-tolerant embedding of quantum circuits on hardware architectures via swap gates. This innovation allows for the implementation and testing of quantum error correction (QEC) circuits on different devices, including those with geometrically local connectivities.

Led by Shao-Hen Chiew, researchers from various institutions have demonstrated the feasibility of this approach using the surface code example. The team’s method involves introducing and proving the fault-tolerance of EPP routing schedules, which can be applied to any device connectivity and quantum circuit. This development is significant as it opens up possibilities for implementing arbitrary circuits on hardware, including protocols that implement logical operations, state preparation, and more.

Companies like IBM and Google, which are already investing heavily in quantum computing, may benefit from this breakthrough. The research has far-reaching implications, providing new insights into the relationship between fault-tolerance and device-implementation details, and paving the way for better architectures of quantum computers and QEC protocols.

The authors propose a general strategy for embedding quantum circuits on devices with connectivity constraints, which is a crucial step towards implementing practical quantum error correction (QEC) protocols. The key innovation lies in introducing and proving the fault-tolerance of EPP (Error Propagation Prevention) routing schedules, which enable the efficient execution of QEC circuits on devices with limited qubit connectivity.

The workflow involves using a classical search algorithm to output an EPP routing schedule, modifying the decoding algorithm accordingly, and simulating the routed circuits under a full-circuit noise model. The authors demonstrate their approach by embedding the surface code circuit onto a heavy-hexagonal lattice device topology, which requires 5 SWAP layers on top of the existing 4 CNOT layers.

The results show that the embedded circuit behaves like a noisier version of the abstract circuit, with an increased error probability contributed by the additional SWAP operations. However, the fault-tolerance properties are preserved, and the threshold for error correction deteriorates by a factor c in the embedded circuit. Similar conclusions are drawn from analyzing other device connectivities.

The implications of this research are far-reaching. Firstly, the approach is compatible with any device connectivity and quantum circuit, making it possible to implement and test QEC circuits on different devices. This flexibility is particularly relevant for current scalable quantum hardware architectures featuring geometrically local connectivities.

Secondly, the embeddings obtained using this approach can result in tolerable deteriorations in performance, rendering them viable in near-term devices available today. The relatively small deterioration factor c suggests that the increase in error rates introduced by this approach will not present a major obstacle for near-term implementations.

Lastly, this research provides new insights into the relationship between fault-tolerance and device-implementation details. By studying the properties of EPP routing schedules, we can gain a deeper understanding of how to design better architectures for quantum computers and QEC protocols.

Overall, this work represents a significant step forward in the development of practical QEC protocols and paves the way for further research into the implementation of fault-tolerant quantum computing on real-world devices.