D-Wave Quantum Inc. has initiated a strategic development initiative to advance cryogenic packaging capabilities for both annealing and gate-model quantum processors. Leveraging expertise from the NASA Jet Propulsion Laboratory, D-Wave has demonstrated superconducting interconnects between chips using a bump-bond process, intended to support scalable control of fluxonium qubits and multichip architectures. The initiative also includes acquiring equipment and developing processes to increase circuit densities in superconducting printed-circuit-board manufacturing, aiming to support larger processors and analog-digital quantum computing technology. D-Wave reports its systems feature QPUs with sub-second response times and currently serves over 100 organizations, having processed more than 200 million problems submitted to its quantum systems.
Key developments:
- D-Wave is partnering with NASA’s Jet Propulsion Laboratory (JPL) to leverage their superconducting bump-bond process expertise
- The company has successfully demonstrated end-to-end superconducting interconnect between chips, which is crucial for scaling both annealing and fluxonium-based gate-model architectures
- They’re acquiring equipment and developing processes to increase circuit densities in superconducting printed-circuit-board (PCB) manufacturing
Technical significance:
Quantum processor packaging requires unique capabilities including compatibility with ultra-low temperatures, extremely low magnetic fields, and fully superconducting interconnects. D-Wave’s approach achieves lower qubit temperatures than most competitors and supports coherence times needed for error-corrected gate-model quantum computing.
According to Dr. Trevor Lanting, D-Wave’s chief development officer, this initiative will help the company extend its leadership position and support its roadmap toward 100,000 qubits. The improved packaging technology is essential for scaling larger quantum processors and supporting analog-digital quantum computing technology.
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