Silicon (110) Confinement Demonstrates Mobility Peak at Cryogenic Temperatures Due to Remote Coulomb Scattering

The pursuit of enhanced performance in silicon nano-devices at extremely low temperatures represents a crucial step forward for future computing technologies. Hsin-Wen Huang, Xi-Jun Fang, and colleagues at National Taiwan University, alongside Edward Chen from Taiwan Semiconductor Manufacturing Company Ltd., and Yuh-Renn Wu, now demonstrate a fundamental shift in how electrons move within these systems as temperatures drop. Their research reveals that, contrary to expectations, electron mobility is not limited by vibrations within the silicon, but instead by a competition between two scattering mechanisms, interactions with distant impurities and imperfections on the material’s surface. This interplay creates a surprising peak in electron mobility, and importantly, highlights a critical design consideration, as high-quality insulating materials, while improving control over the device, can also introduce unwanted scattering that ultimately limits performance. These findings establish essential principles for designing the next generation of cryogenic nano-devices and optimising their efficiency.

Cryogenic Silicon Mobility and Scattering Mechanisms

Researchers investigated two-dimensional electron transport in silicon (110) structures confined by high-κ oxides at cryogenic temperatures. The study aimed to identify the primary scattering mechanisms limiting electron mobility and to explain the observed peak in mobility. The team fabricated silicon-on-insulator structures with thin silicon layers and high-κ dielectric confinement, then performed detailed electrical characterisation at low temperatures. Measurements of electron mobility and resistivity as a function of temperature and carrier density revealed the interplay between various scattering mechanisms, including surface roughness, phonon scattering, and impurity scattering.

The results demonstrate that surface roughness scattering dominates at high carrier densities, while phonon scattering becomes more significant at higher temperatures. Importantly, the study identified the conditions under which a mobility peak emerges, attributing it to a transition in the dominant scattering mechanism and the suppression of impurity scattering at cryogenic temperatures. This understanding of scattering mechanisms is crucial for optimising the performance of nanoscale silicon devices. Through multi-valley Monte Carlo simulations of Si (110) systems, researchers revealed a fundamental shift in electron transport physics at low temperatures.

Phonon scattering becomes negligible, and mobility is instead dictated by a competition between remote Coulomb scattering at low carrier densities and surface roughness scattering at high densities. This competition creates a distinct peak in electron mobility. Furthermore, the team demonstrated a critical design trade-off for high-κ dielectrics like HfO2, noting that while they enhance gate control, they also introduce strong remote Coulomb scattering.

Low Temperature Electron Transport in Silicon Systems

This research investigates electron transport properties in silicon (110) confinement systems at cryogenic temperatures. The study utilises a multi-valley Monte Carlo simulation to model electron behaviour, considering various scattering mechanisms that impact mobility. Key findings include the temperature dependence of scattering, where surface roughness and Coulomb scattering become more dominant as phonon-related scattering diminishes. Comparing SiO2 and HfO2 as gate dielectrics, the research shows that while HfO2 enhances gate control, it also increases remote phonon scattering, presenting a trade-off for device design.

Electron mobility is significantly influenced by inversion layer concentration (Ninv), with a competition between surface roughness and remote Coulomb scattering; lower Ninv favours Coulomb scattering, while higher Ninv increases the impact of surface roughness. At high electric fields, optical phonon emission and intervalley scattering become crucial, influencing electron velocity, with specific peaks in velocity linked to these scattering events. The research identifies that g-type intervalley scattering (related to optical phonon emission) is a key factor in limiting electron velocity at high electric fields. This study provides valuable insights into electron transport in silicon devices at cryogenic temperatures, crucial for optimising device design and materials selection for low-temperature applications, such as quantum computing and advanced sensors. The findings highlight the importance of balancing different scattering mechanisms to achieve optimal performance.

Cryogenic Electron Mobility, Scattering Mechanisms Revealed

Researchers have clarified electron transport mechanisms within silicon nano-devices operating at cryogenic temperatures through detailed multi-valley Monte Carlo simulations. The study demonstrates a fundamental shift in dominant scattering processes as temperature decreases, revealing that phonon scattering becomes negligible while remote Coulomb and surface roughness scattering become critical determinants of electron mobility. Specifically, the team observed a distinct peak in electron mobility resulting from the competition between these two scattering mechanisms, dependent on carrier density. This work also investigated the impact of different dielectric materials, comparing silicon dioxide and hafnium dioxide.

While high-κ dielectrics like hafnium dioxide offer improved gate control, the simulations revealed they also introduce stronger remote phonon scattering, potentially limiting mobility gains. The research highlights a crucial design trade-off for cryogenic devices, necessitating careful consideration of dielectric selection to balance gate control and carrier transport. The team acknowledges that further investigation is needed to explore the impact of different device geometries and materials, with future work potentially focusing on optimising dielectric compositions to minimise phonon scattering while maintaining strong gate control, ultimately leading to enhanced performance in next-generation cryogenic nano-devices.