Researchers led by Professor Takayuki Kawahara from Tokyo University of Science have developed a scalable, fully-coupled annealing processor with 4096 spins. This processor, designed for solving combinatorial optimization problems, divides the calculation into multiple Large Scale Integration (LSI) chips. The technology, which uses 36 22nm CMOS calculation LSI chips and one control Field-Programmable Gate Array (FPGA), outperformed a fully coupled Ising system on a PC by over 2,000 times. The team aims to develop this technology further, targeting a system with the computing power of a 2050-level quantum computer by 2030.
Advancements in Annealing Processors: A Leap in Problem-Solving Speed
Researchers have developed a scalable, fully-coupled annealing processor with 4096 spins, designed to accelerate problem-solving. Annealing processors are specifically engineered to tackle combinatorial optimization problems, which involve finding the optimal solution from a finite set of possibilities. This has practical implications in various fields, including logistics, resource allocation, and drug and material discovery. In the realm of CMOS (Complementary Metal-Oxide-Semiconductor) technology, it is crucial for the components of annealing processors to be fully “coupled.” However, the complexity of this coupling directly influences the scalability of the processors.
The Innovation: A Scalable Processor with Parallelized Capabilities
In a study published in IEEE Access on 30 January 2024, a team led by Professor Takayuki Kawahara from Tokyo University of Science developed and successfully tested a scalable processor that divides the calculation into multiple LSI (Large Scale Integration) chips. This innovation was also presented at the IEEE 22nd World Symposium on Applied Machine Intelligence and Informatics (SAMI 2024) on 25 January 2024. The team’s goal is to achieve advanced information processing directly at the edge, rather than in the cloud, or performing preprocessing at the edge for the cloud.
The Technology: A Scalable Annealing Processor with 4096 Spins
The team created a scalable annealing processor using 36 22nm CMOS calculation LSI chips and one control FPGA (Field-Programmable Gate Array). This technology allows for the construction of large-scale fully coupled semiconductor systems following the Ising model (a mathematical model of magnetic systems) with 4096 spins. The processor incorporates two distinct technologies developed at the Tokyo University of Science. This includes a “spin thread method” that enables 8 parallel solution searches, coupled with a technique that reduces chip requirements by about half compared to conventional methods.
Performance and Future Prospects of the Processor
In terms of power performance ratio, the processor outperformed simulating a fully coupled Ising system on a PC (i7, 3.6GHz) using annealing emulation by 2,306 times. It also surpassed the core CPU and arithmetic chip by 2,186 times. The successful machine verification of this processor suggests the possibility of enhanced capacity. According to Prof. Kawahara, the goal is to develop this technology for a joint research effort targeting an LSI system with the computing power of a 2050-level quantum computer for solving combinatorial optimization problems.
About Tokyo University of Science and Professor Takayuki Kawahara
Tokyo University of Science (TUS) is a renowned and respected university, and the largest science-specialized private research university in Japan. Established in 1881, the university has continually contributed to Japan’s development in science. Professor Takayuki Kawahara is a Professor in the Department of Electrical Engineering at Tokyo University of Science, Japan. His current research is dedicated to sustainable electronics, with a specific focus on low-power artificial intelligence (AI) devices and circuits, sensors, spin current applications, and quantum computing techniques.
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