D Stacked Surface-Code Architecture Achieves Zero SWAP Overhead for Quantum Error Correction

Researchers are tackling a critical challenge in quantum computing , the limitations imposed by mid-circuit measurements in superconducting processors. GunSik Min, IlKwon Sohn, and Jun Heo, from Korea University and the Korea Institute of Science and Technology Information, present a novel 3D stacked surface-code architecture designed to eliminate the need for these problematic measurements and enable truly scalable, fault-tolerant quantum error correction. Their innovative approach bypasses the connectivity issues plaguing existing measurement-free error correction protocols by utilising vertical connections between surface-code layers, achieving zero SWAP overhead and constant-depth operations. This breakthrough not only suppresses unwanted ‘hook’ errors but, according to analytical modelling, promises logical rates significantly faster than both standard and 2D measurement-free surface codes , positioning 3D integration as a vital step towards practical, large-scale quantum computation.

The team achieved this by vertically stacking surface-code patches and utilising transversal couplers, enabling coherent parity mapping and feedback with zero SWAP overhead, a constant-depth operation independent of the code distance, d.

This work establishes a novel architecture where aligned surface-code patches are connected via vertical transversal couplers, facilitating inter-layer operations in O(1) time while maintaining standard 2D stabilizer checks within each layer. A fault-tolerant MFEC protocol was constructed specifically for this 3D architecture, designed to suppress hook errors, a common issue where a single fault can propagate into an uncorrectable multi-qubit error. Experiments utilising an analytical performance model reveal that this 3D architecture surpasses the readout error floor, achieving logical error rates orders of magnitude lower than both standard measurement-based surface codes and 2D MFEC variants in scenarios with slow, noisy measurements. The study unveils 3D integration as a key enabler for scalable measurement-free fault tolerance, paving the way for more robust and efficient quantum computation.
The research addresses a fundamental challenge in quantum computing: the asymmetry between fast gate operations and slower, noisier measurements. Current superconducting hardware boasts gate errors in the 10−3, 10−4 regime, while readout errors remain significantly higher, creating a practical “readout floor” that limits the performance of conventional surface-code cycles. By replacing projective measurements with coherent quantum feedback, MFEC offers a potential solution, but previous implementations suffered from connectivity issues on 2D layouts, requiring SWAP chains of length O(d) to facilitate transversal interactions between logical patches. These SWAP networks increased circuit depth and introduced hook errors, negating the benefits of MFEC.

To circumvent this, the scientists proposed a 3D stacked surface-code architecture, leveraging recent advances in 3D superconducting integration techniques like flip-chip bonding and through-silicon vias. This architecture allows for native transversal connectivity between vertically aligned surface-code patches, eliminating the need for lengthy SWAP chains and achieving constant-depth inter-layer operations. The team constructed a fault-tolerant MFEC protocol tailored to this 3D structure and analysed its performance under realistic noise conditions, demonstrating a substantial reduction in logical error rates compared to both standard measurement-based surface codes and 2D MFEC variants, identifying 3D integration as a critical step towards scalable, measurement-free fault tolerance.

3D Stacked Architecture for Fault-Tolerant Quantum Computation offers

Scientists engineered a novel three-dimensional stacked surface-code architecture to overcome connectivity limitations hindering measurement-free fault-tolerant quantum computation. Existing measurement-free error correction (mfec) protocols demand extensive transversal interactions between logical patches, necessitating SWAP chains scaling with the code distance and introducing significant operational depth and hook errors, a problem this work directly addresses. The team constructed vertical transversal couplers aligning surface-code patches, enabling coherent parity mapping and feedback with zero SWAP overhead, achieving constant-depth inter-layer operations in d dimensions while maintaining local 2D stabilizer checks. Researchers developed a fault-tolerant mfec protocol for the surface code specifically designed to suppress hook errors under realistic noise conditions.

This protocol leverages the 3D architecture to streamline error correction cycles, reducing the complexity associated with traditional measurement-based approaches. An analytical performance model demonstrated that the 3D architecture surpasses the readout floor, attaining logical rates orders of magnitude lower than both standard measurement-based surface codes and two-dimensional mfec variants in scenarios with slow, noisy measurements, identifying 3D integration as crucial for scalable measurement-free fault tolerance. To illustrate the MFEC construction, the study began with a three-qubit bit-flip code, encoding one logical qubit into three physical qubits with logical basis states |0⟩L = |000⟩ and |1⟩L = |111⟩, utilizing stabilizer generators S1 = Z ⊗Z ⊗I and S2 = I ⊗Z ⊗Z. Instead of classical decoding after measuring stabilizers S1 and S2, the researchers coherently mapped stabilizer eigenvalues onto three ancilla qubits initialized in |0⟩⊗3, employing controlled-Z-type circuits decomposed into CNOTs and single-qubit gates.

For instance, CNOT(1 →a1) and CNOT(2 →a1) were applied, followed by single-qubit rotations on a1 and a2 to translate phase information into computational-basis syndromes. The team then implemented a correction unitary of the form Ucorr,bit = X s∈{0,1}3 Ps ⊗Cs, where Ps projects the ancilla register onto syndrome state |s1s2s3⟩ and Cs is an X gate on the appropriate data qubit, implemented via Toffoli and triple-controlled NOT gates controlled by (a1, a2, a3). Gate decomposition was crucial; the Toffoli gate utilized the optimal 6-CNOT decomposition, while the triple-controlled NOT gate required 7 CNOTs. For a distance-3X-error correction round, the researchers calculated 9 CNOTs for the transversal coupling stage, all acting on disjoint pairs and executable in a single time step, and 12 CNOTs for syndrome extraction on the auxiliary patch.

This detailed analysis, focusing on gate counts and depths, provides a concrete basis for comparing the efficiency of 2D and 3D implementations at the logical level0.3D Architecture Enables Measurement-Free. The research introduces a system where vertical connections between aligned surface-code patches enable coherent parity mapping and feedback without the need for extensive SWAP operations, achieving constant-depth inter-layer operations. The key achievement lies in the elimination of SWAP chain overhead, a major issue in two-dimensional measurement-free error correction protocols, by leveraging 3D connectivity as a logical resource. Analytical modelling demonstrates that this 3D architecture surpasses both standard measurement-based surface codes and existing 2D measurement-free variants in scenarios with slow, noisy measurements, suggesting that 3D integration is crucial for scalable measurement-free fault tolerance. The authors acknowledge that their analysis uses a coarse-grained noise model and future work will focus on more detailed circuit-level simulations with realistic decoders and hardware optimisation. Further research will also explore extending the framework to lattice surgery and logical CNOT gates, aiming to create a practical pathway towards high-performance fault-tolerant quantum computing, particularly for systems where measurement errors are dominant.