Superconducting Qubits’ Performance Improved by Optimizing Wiring Design

Superconducting qubits, key components of quantum processors, are vulnerable to dielectric loss, causing noise and dissipation. A study by researchers Nikita S Smirnov, Elizaveta A Krivko, Anastasiya A Solovyova, Anton I Ivanov, and Ilya A Rodionov reveals that over 50% of surface loss in transmon qubits can stem from the wiring of Josephson junctions, reducing the qubit relaxation time. The team used finite-element simulation and experimental results to validate their findings, demonstrating that optimizing the wiring design can enhance the qubit quality factor by up to 20%. This research provides valuable insights for future qubit design and optimization.

What is the Impact of Wiring Surface Loss on Superconducting Transmon Qubits?

Superconducting qubits, the building blocks of quantum processors, are susceptible to dielectric loss, which leads to noise and dissipation. These qubits are typically designed as large capacitor pads connected to a nonlinear Josephson junction or SQUID by a superconducting thin metal wiring. Recent research by Nikita S Smirnov, Elizaveta A Krivko, Anastasiya A Solovyova, Anton I Ivanov, and Ilya A Rodionov has shown that more than 50% of surface loss in transmon qubits can originate from the wiring of these Josephson junctions, limiting the qubit relaxation time.

The researchers used finite-element simulation and experimental results to confirm their findings. They also extracted dielectric loss tangents of qubit elements and demonstrated that the dominant surface loss of wiring can occur for real qubits designs. By optimizing the wiring design, they were able to improve the qubit quality factor by up to 20%.

How Does Dielectric Loss Affect Quantum Processors and Simulators?

Quantum processors and simulators, which can comprise tens or even hundreds of superconducting qubits, have been demonstrated recently. However, quantum gates errors hinder the further size and complexity growth of superconducting circuits and quantum algorithms. Reducing two-qubit gate errors to less than 0.1 opens a practical way to implement quantum error correction codes. However, superconducting quantum bits have natural internal sources of noise and decoherence, which limit quantum gates fidelity.

A significant part of qubits loss is due to microscopic tunneling defects, which form parasitic two-level quantum systems (TLS) and resonantly absorb electric energy from the qubit mode, dissipating it into phonons or quasiparticle bath. These defects reside in the interfaces and surface native oxides around qubit electrodes. This source of qubit loss could be mitigated by reducing the amounts of lossy dielectrics, minimizing Josephson junction area, using better materials, and defect-free fabrication techniques.

What is the Role of Josephson Junctions and SQUIDs in Qubit Relaxation?

A superconducting transmon qubit can be imagined as a nonlinear LC oscillator, where the Josephson junction or SQUID define a nonlinear inductance and the superconducting metal pads define a capacitor. These junctions or SQUID loop electrodes have to be electrically connected to the capacitor pads, a connection commonly realized as a thin metal wire. The design of the frequency-tunable two-padded floating transmon qubit, which is investigated in this study, is shown in Fig 1a.

To improve qubit relaxation time, dilute an electromagnetic field, and lower interfaces participation ratio, the gap between the capacitor pads is increased. However, this requires long Josephson junction connecting wires. In the case of a flux-tunable qubit, the wiring length becomes even longer to form a SQUID loop and move it closer to the gap edge and flux-control line.

How Does the Gap Width Affect Qubit Performance?

As the gap width increases, the capacitor pads participation ratio decreases, but the leads and SQUID participation ratios increase. When the gap width is more than 110 µm, then the participation ratio of the leads with SQUID become dominant, and further gap widening is impractical. Thus, a relaxation time of a properly designed qubit is limited by the leads and SQUID loss if their loss tangent is comparable to the capacitor pads one. To further increase the qubit relaxation time, optimization of the leads width is required.

The researchers calculated the participation ratios using a similar method as in Ref25 but with modifications to be able to analyze asymmetrically located SQUID loop with long leads. When they calculate the participation ratios of qubit components, they consider bulk superconductor and crystalline dielectric to be lossless.

What are the Future Implications of this Research?

In order to mitigate surface dielectric loss in qubits, previous work was primarily focused on capacitor pads design modifications, investigation of Josephson junction contribution with so-called bandages, and fabrication improvements. Despite the remarkable results achieved in these works, contribution from the Josephson junction wiring has mainly remained ignored.

This study has analytically predicted that a significant fraction of surface loss comes from the wiring that connects the qubit to the capacitor. The researchers experimentally studied the contribution of leads and SQUID to the overall qubit surface dielectric loss. They performed finite-element electromagnetic simulations of the transmon qubits with different wiring designs, providing valuable insights for future qubit design and optimization.