Spintronic Ising Machine Achieves Ultra-Fast, Low-Power Combinatorial Optimisation.

A spintronic Ising machine, fabricated on a chip using voltage-controlled magnetoresistive random access memory, achieves spin updates with sub-nanosecond latency and 40 femtojoule energy consumption. This represents a 1000-fold improvement over current-driven implementations and outperforms conventional processors by six to seven orders of magnitude when solving complex combinatorial optimisation problems.

The pursuit of more efficient computation is driving exploration beyond conventional computer architectures. Researchers are increasingly investigating physics-inspired methods, notably Ising machines, to address complex combinatorial optimisation problems (COPs) that challenge traditional systems. A team led by Yihao Zhang and Weisheng Zhao from Beihang University, in collaboration with Albert Lee, Zheng Zhu, and Di Wu from InstonTech, and Lei Gao from Empyrean Technology Co., Ltd., report a novel implementation of an Ising machine utilising voltage-controlled magnetoresistive random access memory. Their work, detailed in the article ‘An Ultra-Low Power and Fast Ising Machine using Voltage-Controlled Magnetoresistive Random Access Memory’, demonstrates a significant reduction in both latency and energy consumption – achieving spin updates in under 1 nanosecond with an energy cost of less than 40 femtojoules – and showcases superior performance on practical problems in electronic design automation compared to conventional and graphics processing units.

Voltage-Controlled Spintronic Ising Machine Demonstrates Enhanced Optimisation Performance

This research details the development and demonstration of a novel chip-level Ising machine, utilising voltage-controlled magnetoresistive random access memory (VC-MRAM) to address computationally intensive combinatorial optimisation problems (COPs). The system represents a departure from conventional von Neumann architectures, leveraging the inherent parallelism of spintronic devices for accelerated computation and improved energy efficiency. Researchers fabricated a custom VC-MRAM chip, implementing Ising spins – discrete units representing magnetic states – through the voltage-controlled magnetic anisotropy effect within magnetic tunnel junctions (MTJs). This allows dynamic configuration and efficient computation. A field-programmable gate array (FPGA) serves as the control system, managing problem definition, Ising model mapping, chip configuration, and result readout, creating an adaptable computational platform.

The researchers successfully mapped real-world COPs, specifically global routing and layer assignment in very large scale integration (VLSI) design, onto the Ising model. The FPGA configures the VC-MRAM chip to represent the problem’s parameters, allowing the system to evolve towards a low-energy state corresponding to the optimal solution, mirroring the behaviour of physical systems seeking minimal energy. The FPGA then reads the final spin states, interpreting them as the solution to the original COP, completing the computational cycle and providing actionable results. This approach achieves a spin update latency below 1 nanosecond and consumes under 40 femtojoules per update.

Performance evaluations demonstrate high success rates in solving the VLSI design problems, confirming the system’s effectiveness in tackling complex computational challenges. The system exhibits an energy efficiency of 25,000 solutions per second per watt, surpassing state-of-the-art CPUs and graphics processing units by six and seven orders of magnitude, establishing a new benchmark for energy-efficient computation. Robustness to device variations within the VC-MRAM chip ensures reliable performance despite imperfections, demonstrating the system’s resilience and practicality for real-world applications. This work establishes voltage-controlled spintronics as a promising pathway towards next-generation physics-inspired machine intelligence, offering a potential paradigm for ultra-low-power, high-speed, and scalable computation.

Extended data confirms the influence of penalty coefficients on solution accuracy, demonstrating control over the system’s performance and enabling fine-tuning for specific problem sets. The system overcomes limitations of conventional architectures by exploiting the inherent parallelism of spintronic devices and minimising energy consumption.